Abstract: A CDMA receiving apparatus includes a receiving section, a memory circuit, an estimating circuit and a generating circuit. The receiving section generates a baseband signal from a received radio signal, searches a path having the highest correlation with the received radio signal, generates a path delay quantity for the searched path and generates a demodulated signal as an object signal from the baseband signal based on the path delay quantity. The memory circuit stores at least one SIR value as a previous SIR value. The estimating circuit estimates the SIR value from the object signal and stores the estimated SIR value in the memory circuit. The generating circuit generates a TPC (transmission power control) bit signal for controlling transmission power from the estimated SIR value and the previous SIR value stored in the memory circuit based on the path delay quantity and a reference SIR value.

Abstract: Disclosed is a CDMA base station transmission device having: a first spread multiplex synthesis unit that spreads and multiplexes transmit data of a predetermined number of users to be selected from a plurality of users; and a second spread multiplex synthesis unit that is additionally provided when the number of users increases. The first spread multiplex synthesis unit is provided with a first multiplex synthesis part inside the unit, and the first multiplex synthesis part adds the spread-multiplexed data of the first spread multiplex synthesis unit and the spread-multiplexed data of the second spread multiplex synthesis unit, D/A-converts the added spread-multiplexed data, modulates it into radio frequency band, transmits it through the antenna.

Abstract: A base station transmitter for a CDMA system which can quickly reflect an amplitude controlling signal from a mobile station in transmission power control of the base station. The transmitter has a plurality of channel signal processing units which are provided for each communication channel and each of which converts an amplitude signal and a transmission signal into a serial signal. The transmission signal represents information to be transmitted and the amplitude signal is a signal for directing whether an amplitude of the transmission signal is increased or decreased. In the serial signal, one or more dummy bits are inserted between the transmission signal and the amplitude signal. The serial signal is then separated into the transmission signal and the amplitude signal. Each of the separated transmission signals is spread modulated with a corresponding spread code, and the spread modulated signals are combined into a combined spread signal on the basis of respective amplitude signals.

Abstract: A CDMA receiving apparatus includes a receiving section, a memory circuit, an estimating circuit and a generating circuit. The receiving section generates a baseband signal from a received radio signal, searches a path having the highest correlation with the received radio signal, generates a path delay quantity for the searched path and generates a demodulated signal as an object signal from the baseband signal based on the path delay quantity. The memory circuit stores at least one SIR value as a previous SIR value. The estimating circuit estimates the SIR value from the object signal and stores the estimated SIR value in the memory circuit. The generating circuit generates a TPC (transmission power control) bit signal for controlling transmission power from the estimated SIR value and the previous SIR value stored in the memory circuit based on the path delay quantity and a reference SIR value.

Abstract: The CDMA synchronous capture circuit which calculates correlation values by using a part of received data for the detection of the peak position, and then decides an upper temporal peak position where the correlation values are great. The CDMA synchronous capture circuit of the present invention calculates the remaining correlation values, giving priority over the temporal peak position, by using the remaining received data, and finally decides a peak value from the correlation level by adding the above-mentioned two kinds of correlation values.

Abstract: A CDMA synchronous acquisition circuit for receiving a CDMA signal and performing synchronous acquisition on the CDMA signal, comprises a receiving unit for receiving a signal and decoding the received signal to a reception base band signal which is spread-modulated in a CDMA mode, a correlation circuit for calculating a correlation value for the received base band signal every timing within one chip of a spread code by a correlator, and means for detecting the maximum value of the correlation value to estimate the spread code generation timing of a spread-modulated transmission base band signal within a precision of one chip of the spread code, wherein the correlator includes offset removing means for removing a DC offset component due to unbalance of the code balance of the spread code.

Abstract: A CDMA synchronous acquisition circuit for receiving a CDMA signal and performing synchronous acquisition on the CDMA signal, comprises a receiving unit for receiving a signal and decoding the received signal to a reception base band signal which is spread-modulated in a CDMA mode, a correlation circuit for calculating a correlation value for the received base band signal every timing within one chip of a spread code by a correlator, and means for detecting the maximum value of the correlation value to estimate the spread code generation timing of a spread-modulated transmission base band signal within a precision of one chip of the spread code, wherein the correlator includes offset removing means for removing a DC offset component due to unbalance of the code balance of the spread code.

Abstract: A receiver removes a direct current (DC) offset component from a received Code Division Multiple Access (CDMA) spread spectrum signal. The DC offset is attributed to both spreading code imbalance as well as conversion between analog and digital formats. In operation, received data is de-spread using an appropriate de-spreading code. Thereafter, a DC offset removing circuit employs a positive/negative counter counting each occurrence of positive and negative chips to produce a chip imbalance for each chip in the spreading code. The measured imbalance is multiplied by the received data signal, an RF component of this multiplied output is removed by a low-pass filter, and thereafter, the signal is again multiplied by the chip imbalance. The DC offset components in the received signal are removed by subtracting the second multiplied signal from the received data signal.

Abstract: In a signal reception system comprising an adaptive filter having a plurality of filter coefficients and producing a filtered signal, a differential detection circuit for carrying out differential detection operation by the use of a delayed signal wherein the filtered signal is delayed, and an error signal generation circuit for generating an error signal, the adaptive filter adjusts the plurality of filter coefficients in accordance with the error signal. An error signal control circuit has a threshold value and supplies the error signal to the adaptive filter only when the delayed signal has a signal value which is higher than the threshold value.