Patents by Inventor Shvetal K. Patel

Shvetal K. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parallel/pipeline VLSI architecture for a low-delay CELP coder/decoder
    Patent number: 6314393
    Abstract: An integrated circuit for processing a speech signal in accordance with a CELP standard includes a plurality of processing elements coupled to a data bus in parallel. Each processing element includes a multiplier and an accumulator. The integrated circuit further includes an auxiliary processing element, which is also coupled to the data bus and has a division unit and a comparator. The plurality of processing elements and the auxiliary processing element are also coupled in a pipeline formation.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: November 6, 2001
    Assignee: Hughes Electronics Corporation
    Inventors: Yue-Peng Zheng, Shvetal K. Patel, Kumar Swaminathan