Patents by Inventor Shwang-Ming Cheng
Shwang-Ming Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7564136Abstract: A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.Type: GrantFiled: February 24, 2006Date of Patent: July 21, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Ling Yeh, Chen-Hua Yu, Keng-Chu Lin, Tien-I Bao, Shwang-Ming Cheng
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Patent number: 7405481Abstract: In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.Type: GrantFiled: December 3, 2004Date of Patent: July 29, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Chu Lin, Yung-Cheng Lu, Shwang-Ming Cheng
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Patent number: 7314828Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.Type: GrantFiled: July 19, 2005Date of Patent: January 1, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Chu Lin, Chen-Hua Yu, Ching-Ya Wang, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Cheng
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Publication number: 20070202676Abstract: A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Ming Yeh, Chen-Hua Yu, Keng-Chu Lin, Tien-I Bao, Shwang-Ming Cheng
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Publication number: 20070161230Abstract: A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).Type: ApplicationFiled: January 10, 2006Publication date: July 12, 2007Inventors: I-I Chen, Tien-I Bao, Shwang-Ming Cheng, Chen-Hua Yu
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Publication number: 20070020952Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.Type: ApplicationFiled: July 19, 2005Publication date: January 25, 2007Inventors: Keng-Chu Lin, Chen-Hua Yu, Ching-Ya Wang, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Cheng
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Patent number: 7160800Abstract: Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.Type: GrantFiled: January 7, 2005Date of Patent: January 9, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhen-Cheng Wu, Cheng-Hung Chang, Yu-Lien Huang, Shwang-Ming Cheng
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Patent number: 7135402Abstract: A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CxHy layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.Type: GrantFiled: February 1, 2005Date of Patent: November 14, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Chu Lin, Shwang-Ming Cheng, Ming Ling Yeh, Tien-I Bao
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Patent number: 7115974Abstract: In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.Type: GrantFiled: July 21, 2004Date of Patent: October 3, 2006Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.Inventors: Zhen-Cheng Wu, Hung Chun Tsai, Da-Wen Lin, Weng Chang, Shwang-Ming Cheng, Mong Song Liang
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Publication number: 20060172531Abstract: A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CXHY layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.Type: ApplicationFiled: February 1, 2005Publication date: August 3, 2006Inventors: Keng-Chu Lin, Shwang-Ming Cheng, Ming Yeh, Tien-I Bao
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Publication number: 20060172530Abstract: A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.Type: ApplicationFiled: February 1, 2005Publication date: August 3, 2006Inventors: Shwang-Ming Cheng, Ming Yeh, Tien-I Bao, Keng-Chu Lin
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Publication number: 20060154481Abstract: Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.Type: ApplicationFiled: January 7, 2005Publication date: July 13, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zhen-Cheng Wu, Cheng-Hung Chang, Yu-Lien Huang, Shwang-Ming Cheng
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Publication number: 20060118921Abstract: In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.Type: ApplicationFiled: December 3, 2004Publication date: June 8, 2006Inventors: Keng-Chu Lin, Yung-Cheng Lu, Shwang-Ming Cheng
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Publication number: 20050236694Abstract: In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.Type: ApplicationFiled: July 21, 2004Publication date: October 27, 2005Inventors: Zhen-Cheng Wu, H. Tsai, Da-Wen Lin, Weng Chang, Shwang-Ming Cheng, Mong Liang