Abstract: An ILD dielectric layer stack and method for forming the same, the method includes a semiconductor substrate including CMOS transistors with gate electrode portions; depositing a first layer including phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and forming metal filled local interconnects extending through a thickness portion of the first and second layers.

Abstract: An ILD dielectric layer stack and method for forming the same, the method includes a semiconductor substrate including CMOS transistors with gate electrode portions; depositing a first layer including phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and forming metal filled local interconnects extending through a thickness portion of the first and second layers.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.

Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.

Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract: Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.

Abstract: Low-strength plasma treatment for interconnects is disclosed. A low k dielectric-metal interconnect is formed that has a top surface, via a damascene process, such as a single- or a dual-damascene process. The top surface of the low k dielectric-metal interconnect is low-power plasma treated to substantially cure any damage to the top surface resulting from the damascene process. Such damage may include the entrapment of metal ions, such as copper ions where the metal of the interconnect is copper, and chemical-mechanical planarization (CMP) materials resulting from the CMP employed during the damascene process, within the top surface of the low k dielectric-metal interconnect. The low-power plasma used may be helium plasma.

Abstract: A method is provided for forming a blocking layer in a multilayer semiconductor device for blocking diffusion of a chemical species including the steps of providing an insulating layer including a target surface for forming a metal nitride layer thereon said insulating layer forming a portion of a multilayer semiconductor device; treating the target surface with an RF generated plasma to cause a density increase over a thickness adjacent to and including a target surface sufficient to reduce a diffusion rate of chemical species therethrough; forming at least one metal nitride layer over the target surface; and, carrying out a photolithographic process wherein the surface of the at least one metal nitride layer is patterned for etching.

Abstract: A method is provided for forming a blocking layer in a multilayer semiconductor device for blocking diffusion of a chemical species including the steps of providing an insulating layer including a target surface for forming a metal nitride layer thereon said insulating layer forming a portion of a multilayer semiconductor device; treating the target surface with an RF generated plasma to cause a density increase over a thickness adjacent to and including a target surface sufficient to reduce a diffusion rate of chemical species therethrough; forming at least one metal nitride layer over the target surface; and, carrying out a photolithographic process wherein the surface of the at least one metal nitride layer is patterned for etching.

Abstract: A method of fabricating a CVD low-k SiOCN material. The first embodiment comprising the following steps. MeSiH3, N2O, and N2 are reacted at a molar ratio of from about 1:5:10 to 1:10:15, at a plasma power from about 0 to 400 W to deposit a final deposited film. The final deposited film is treated to stabilize the final deposited film to form a CVD low-k SiOCN material. The second embodiment comprising the following steps. A starting mixture of MeSiH3, SiH4, N2O, and N2 is reacted at a molar ratio of from about 1:1:5:10 to 1:5:10:15, in a plasma in a helium carrier gas at a plasma power from about 0 to 400 W to deposit a CVD low-k SiOCN material.

Abstract: A method to reduce via poisoning in low-k copper dual damascene interconnects through ultraviolet (UV) irradiation of the damascene structure is disclosed. This is accomplished by irradiating the insulative layers each time the layers are etched to form a portion of the damascene structure. Thus, irradiation is performed once after the forming of a trench or a via, and again for the second time when the insulative layers are etched to form the remaining trench or via. The trench and hole openings of the dual damascene structure are exposed to UV light in a dry ozone environment, which then favorably alters the surface characteristics of the low-k dielectric walls which are normally hydrophobic. Hence, during etching, moisture is not absorbed into the walls.