Patents by Inventor Shweta BANSAL

Shweta BANSAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for power analysis for design logic circuit with irregular clock
    Patent number: 11443087
    Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 13, 2022
    Assignee: SYNOPSYS, INC.
    Inventors: Alexander John Wakefield, Jitendra Gupta, Vaibhav Jain, Rahul Jain, Shweta Bansal
  • SYSTEM AND METHOD FOR POWER ANALYSIS FOR DESIGN LOGIC CIRCUIT WITH IRREGULAR CLOCK
    Publication number: 20200364391
    Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Applicant: Synopsys, Inc.
    Inventors: Alexander John WAKEFIELD, Jitendra GUPTA, Vaibhav JAIN, Rahul JAIN, Shweta BANSAL