Abstract: This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.

Abstract: This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.