Abstract: Operation of an Enhanced Data Buffer and Intelligent NV Controller for Simultaneous DRAM and Flash Memory Access has been disclosed. In one implementation a host can operate at full DRAM speed to a DIMM having thereon a NV Controller, DRAM, and flash memory.

Abstract: A method is provided for issuing subcommands to a memory module using unassigned bits in a memory control protocol. A buffer component within the memory module receives the subcommands and modifies a state of the memory module accordingly. This allows, for example, selectively powering down individual ranks of the memory module (e.g., an LRDIMM memory module). Unassigned bits in a JEDEC-compliant ZQ calibration command set may be used for implementing such subcommands.

Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Abstract: A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes. In a first mode, the memory buffer circuit is configured to interface to a first type of memory device, is configured to enable an input circuit of the memory buffer circuit, and is configured to drive on a terminal of a memory interface of the memory buffer circuit a version of a signal received by the input circuit during a memory operation. In a second mode, the memory buffer circuit is configured to interface to the first type of memory device, is configured to disable the input circuit, and is configured to drive a signal on the terminal during the memory operation.

Abstract: A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes. In a first mode, the memory buffer circuit is configured to interface to a first type of memory device, is configured to enable an input circuit of the memory buffer circuit, and is configured to drive on a terminal of a memory interface of the memory buffer circuit a version of a signal received by the input circuit during a memory operation. In a second mode, the memory buffer circuit is configured to interface to the first type of memory device, is configured to disable the input circuit, and is configured to drive a signal on the terminal during the memory operation.

Abstract: A first DRAM device comprises a first input connected to a first trace line to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line to receive the address signal and a second input to receive the operating voltage. A first signal termination structure is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A memory device may be implemented to respond to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for the memory device. For example, a memory device may include a memory array and a mode register configured to store a value indicating a current burst length. The memory array may be configured to perform a first burst access having a first burst length in response to receiving a first command encoding and to perform a second burst access having a second burst length, which does not equal the current burst length, in response to receiving a second command encoding. A memory controller may be implemented to generate to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for a targeted memory device.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, at least one of the memory modules includes a cache for storing data stored in a system memory.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.