Patents by Inventor Shwu-Jen Jeng
Shwu-Jen Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8754446Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.Type: GrantFiled: August 30, 2006Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, Shwu-Jen Jeng, Byeong Y. Kim, Hasan M. Nayfeh
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Patent number: 8084788Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.Type: GrantFiled: October 10, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Judson Robert Holt, Abhishek Dube, Eric C. T. Harley, Shwu-Jen Jeng, Jeremy J Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
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Publication number: 20100090288Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.Type: ApplicationFiled: October 10, 2008Publication date: April 15, 2010Applicant: International Business Machines CorporationInventors: Judson R. Holt, Abhishek Dube, Eric C.T. Harley, Shwu-Jen Jeng, Jeremy J. Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
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Patent number: 7642569Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: GrantFiled: February 5, 2009Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: David R. Greenberg, Shwu-Jen Jeng
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Publication number: 20090134429Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: ApplicationFiled: February 5, 2009Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David R. Greenberg, Shwu-Jen Jeng
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Patent number: 7491623Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.Type: GrantFiled: August 20, 2007Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, Shwu-Jen Jeng, Byeong Y. Kim, Hasan M. Nayfeh
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Patent number: 7491617Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: GrantFiled: June 18, 2007Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: David R. Greenberg, Shwu-Jen Jeng
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Publication number: 20080121931Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.Type: ApplicationFiled: August 30, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaomeng Chen, Shwu-Jen Jeng, Byeong Y. Kim, Hasan M. Nayfeh
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Publication number: 20080057673Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.Type: ApplicationFiled: August 20, 2007Publication date: March 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaomeng CHEN, Shwu-Jen JENG, Byeong Y. KIM, Hasan M. NAYFEH
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Publication number: 20070241428Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: ApplicationFiled: June 18, 2007Publication date: October 18, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Greenberg, Shwu-Jen Jeng
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Patent number: 7253070Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: GrantFiled: July 5, 2006Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: David R. Greenberg, Shwu-Jen Jeng
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Publication number: 20060249814Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: ApplicationFiled: July 5, 2006Publication date: November 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Greenberg, Shwu-Jen Jeng
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Patent number: 7075126Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: GrantFiled: February 27, 2004Date of Patent: July 11, 2006Assignee: International Business Machines CorporationInventors: David R. Greenberg, Shwu-Jen Jeng
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Patent number: 7022246Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.Type: GrantFiled: January 6, 2003Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Shwu-Jen Jeng, Michael F. Lofaro, Christopher M. Schnabel, Kenneth J. Stein
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Publication number: 20050191911Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: ApplicationFiled: February 27, 2004Publication date: September 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Greenberg, Shwu-Jen Jeng
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Patent number: 6927476Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.Type: GrantFiled: September 25, 2001Date of Patent: August 9, 2005Assignee: Internal Business Machines CorporationInventors: Gregory G. Freeman, Seshadri Subbanna, Basanth Jagannathan, Kathryn T. Schonenberg, Shwu-Jen Jeng, Kenneth J. Stein, Jeffrey B. Johnson
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Publication number: 20050095787Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.Type: ApplicationFiled: November 19, 2004Publication date: May 5, 2005Applicant: International Business Machines CorporationInventors: Arne Ballantine, Donna Johnson, Matthew Gallagher, Peter Geiss, Jeffrey Gilbert, Shwu-Jen Jeng, Robb Johnson
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Patent number: 6787427Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.Type: GrantFiled: October 1, 2003Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
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Publication number: 20040130434Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.Type: ApplicationFiled: January 6, 2003Publication date: July 8, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. Chinthakindi, Shwu-Jen Jeng, Michael F. Lofaro, Christopher M. Schnabel, Kenneth J. Stein
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Publication number: 20040063293Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.Type: ApplicationFiled: October 1, 2003Publication date: April 1, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell