Patents by Inventor Shyam Chandra

Shyam Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210154079
    Abstract: Lack of gravity is a cause of major health concerns for astronauts travelling or living in space. The systems, in accordance with the embodiments of the invention, provide Artificial Gravity. The users or subjects experience Artificial Gravity while exercising in an environment without gravity, such as space. Another embodiment includes chambers shielded by multilayer magnetic toroid and multilayer soft magnetic layered clothing that shields astronauts from radiation and stray magnetic fields while providing a gravitational (artificial gravity) effect.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 27, 2021
    Inventor: Shyam Chandra DAS
  • Patent number: 9910818
    Abstract: A local device, such as a field-programmable gate array, has a local state machine and a local interface component for communicating with a remote device that implements a remote state machine. The local interface component receives a new set of incoming data from the remote device and determines whether the new set is good data or bad data. If good data, then the local interface component causes the new set of data to transmitted internally for use by the local state machine. If bad data, then the local interface component does not forward the new set of data to the local state machine, which instead continues to use a previously received set of good data. Although the clock rate of the local and remote state machines may differ from the frame rate of the local interface component, their operations are nevertheless synchronized.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: March 6, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventors: Stephen O'Connor, Shyam Chandra, Robert Bartel
  • Publication number: 20150095534
    Abstract: A local device, such as a field-programmable gate array, has a local state machine and a local interface component for communicating with a remote device that implements a remote state machine. The local interface component receives a new set of incoming data from the remote device and determines whether the new set is good data or bad data. If good data, then the local interface component causes the new set of data to transmitted internally for use by the local state machine. If bad data, then the local interface component does not forward the new set of data to the local state machine, which instead continues to use a previously received set of good data. Although the clock rate of the local and remote state machines may differ from the frame rate of the local interface component, their operations are nevertheless synchronized.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Lattice Semiconductor Corporation
    Inventors: Stephen O'Connor, Shyam Chandra, Robert Bartel
  • Patent number: 8122277
    Abstract: In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 21, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventors: Shyam Chandra, Om Agrawal, Ludmil Nikolov, Harald Weller, Douglas Morse
  • Patent number: 8112656
    Abstract: In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 7, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventors: Shyam Chandra, Om Agrawal, Ludmil Nikolov, Harald Weller, Douglas Morse
  • Patent number: 7657773
    Abstract: In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: February 2, 2010
    Assignee: Lattice Semiconductor Corporation
    Inventors: Shyam Chandra, Om Agrawal, Ludmil Nikolov, Harald Weller, Douglas Morse
  • Patent number: 5778514
    Abstract: Metal-in-the-gap (MIG) transducing head formed on a substrate for use in a magnetic storage device for writing and/or reading data in the form of magnetic flux onto and/or from tracks on magnetic media which moves relative to the head, formed by batch processing techniques. In preferred embodiment, MIG head is write head and further includes magnetoresistive read head, all on a common substrate.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: July 14, 1998
    Assignee: DAS Devices, Inc.
    Inventor: Shyam Chandra Das
  • Patent number: 4972287
    Abstract: A new read/write head for use in a mass storage device in a digital data processing system. The head is a thin-film head having a solenoidal coil around one or both of the pole pieces. Sets of planar conductive traces are formed on planar layers of insulating material on opposing sides of a pole piece, with vias connecting the ends of selected traces to thereby form a solenoidal coil around the pole piece.
    Type: Grant
    Filed: December 8, 1989
    Date of Patent: November 20, 1990
    Assignee: Digital Equipment Corp.
    Inventor: Shyam Chandra Das