Abstract: The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming a masking layer over a semiconductor substrate such that the gate conductor is substantially covered by the masking layer. The masking layer is preferably planarized using any of a variety of well known techniques. After planarization of the masking layer, the masking layer is etched such that an upper surface of the gate conductor is exposed. A silicide layer is preferably formed upon the upper surface of the gate conductor. The masking layer prevents the concurrent formation of silicide upon the source/drain regions.

Abstract: The present method and apparatus provides a thin layer of oxynitride over a device including a patterned metal layer, application of a planarizing SOG layer over the thin oxynitride layer, removal of thin portions of the SOG layer by etching to expose portions of the thin oxynitride layer, and application of a thick oxynitride layer to form a strong bond with the thin oxynitride layer. A thin nitride layer, transparent to UV light, may then be applied to the resulting structure prior to application of plastic packaging material.

Abstract: An etch process utilizing Cl.sub.2 /He chemistry for use in a silicon integrated circuit manufacturing process. The etch is a highly nitride selective, anisotropic etch. The manufacturing process in which the Cl.sub.2 /He etch is employed includes steps of oxidizing a surface of a silicon wafer; depositing a first polycrystalline silicon on the wafer surface; depositing a silicon nitride-silicon dioxide layer on the wafer surface; depositing a silicon nitride spacer on the wafer; etching with Cl.sub.2 /He chemistry to remove essentially all of the silicon nitride spacer except for bitline remnants (i.e., stringers) of the silicon nitride spacer atop silicon dioxide; depositing a second polycrystalline silicon atop the etched wafer; and selectively removing portions of said second polycrystalline silicon from the wafer. The bitline remnants of the silicon nitride, i.e., stringers, are not conductive. The Cl.sub.

Abstract: A wafer surface cleaning method is provided comprising immersion of the wafer in a H.sub.2 O:NH.sub.4 OH:H.sub.2 O.sub.2 solution at a temperature less than 65.degree. C. prior to formation of a thin oxide such as a tunnel oxide or gate oxide. Immersion of the wafer in a sub-65.degree. C. NH.sub.4 OH results in a smoother wafer surface that increase the charge-to-breakdown (Q.sub.BD) of the subsequently formed oxide. In the tunnel oxide embodiment, the lower temperature solution also reduces the oxide etch rate of the solution enabling a minimum overgrowth of gate oxide which, in turn, enables the addition of an in situ growth temperature anneal of the gate oxide without altering other process parameters.

Abstract: A reference cell in a nonvolatile memory is electrically erasable and the electrically erasable character of the memory is exploited to expand the voltage range over which a differential amplifier is useful for sensing the state of a bit. Selected elements of a reference cell are electrically erased and reprogrammed for accurately tuning the sensing of multiple data states in a memory cell. For example, 64 or more data states may be tuned so that a single megabyte of memory is allocated to store six megabytes of information.

Abstract: The present method and apparatus provides a thin layer of oxynitride over a device including a patterned metal layer, application of a planarizing SOG layer over the thin oxynitride layer, removal of thin portions of the SOG layer by etching to expose portions of the thin oxynitride layer, and application of a thick oxynitride layer to form a strong bond with the thin oxynitride layer. A thin nitride layer, transparent to UV light, may then be applied to the resulting structure prior to application of plastic packaging material.

Abstract: A storage control circuit determines a programmed threshold voltage V.sub.tP of a storage cell in which the transistor threshold voltages V.sub.tT of the cell may overlap while the logical threshold voltages V.sub.tL remain distinct. In one embodiment, sixteen distinctive levels are stored in a storage cell within a 2.5 V range so that a single memory cell supplies four bits of information storage per cell, quadrupling the memory capacity per cell as compared to conventional single-bit storage cells. In an embodiment, a nonvolatile memory circuit includes a nonvolatile memory array with a plurality of memory cells and a plurality of decoders connected to the nonvolatile memory array. The plurality of decoders decode addresses to the nonvolatile memory array.

Abstract: An improved method is provided for fabricating a metallization structure upon a semiconductor wafer. The method performs nitridation upon a sputter-deposited Ti layer over junction regions prior to silicidation thereof. Further, nitridation and silicidation are each performed at controlled amounts within the Ti layer overlying field dielectric regions, also included in the semiconductor wafer. Nitridation and silicidation thereby occur during a three-step anneal process of a previously deposited Ti layer. The three anneal steps are carried forward at separate and distinct temperatures, wherein the first anneal temperature is followed by a second, higher anneal temperature, and wherein the second anneal cycle is followed by a third anneal cycle of higher temperature than the first or second anneal temperatures. The resulting TiN/Ti/TiSi.sub.