Abstract: Translation between virtual memory addresses and physical memory addresses is mediated by a program counter indexed table holding virtual and corresponding physical addresses. In some embodiments, this table can be accessed early in the fetch cycle and avoid likely TLB misses.

Abstract: An eyewear device comprising (1) an eyewear frame dimensioned to be worn by a user, (2) circuitry coupled to the eyewear frame, the circuitry comprising a hardware accelerator configured to (A) identify an input that indicates one or more features of an instance of graphical imagery and (B) perform, based at least in part on the input, one or more lookup operations via one or more arrays to obtain an output used to approximate computation of a rendering of the instance of graphical imagery, and (3) a display coupled to the eyewear frame and configured to present the rendering of the instance of graphical imagery to the user. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Translation between virtual memory addresses and physical memory addresses is mediated by a program counter indexed table holding virtual and corresponding physical addresses. In some embodiments, this table can be accessed early in the fetch cycle and avoid likely TLB misses.

Abstract: A computer architecture provides a pre-sending of memory blocks from a lower level memory hierarchy component to a higher level memory hierarchy component using a table linking a set of memory blocks holding instructions that are executed in different fragments of a program. The table is used to pre-send memory blocks to the higher level memory hierarchy component in anticipation of their use by a processor executing the program.

Abstract: A computer architecture provides a pre-sending of memory blocks from a lower level memory hierarchy component to a higher level memory hierarchy component using a table linking a set of memory blocks holding instructions that are executed in different fragments of a program. The table is used to pre-send memory blocks to the higher level memory hierarchy component in anticipation of their use by a processor executing the program.

Abstract: A technique optimizes the distribution of authenticated users among a plurality of broadcast domains, such as virtual local area networks (VLAN). Users are dynamically assigned to different broadcast domains based on various factors, including but not limited to the number of authenticated users already participating in each broadcast domain, the available bandwidth in each broadcast domain, user classes associated with users participating in each broadcast domain, etc. Based on one or more of these factors, authenticated users are optimally distributed (“load balanced”) among the plurality of broadcast domains, thereby reducing the amount of broadcast traffic and configuration within each domain.