Abstract: A method for fabricating an inductor module includes steps of: providing a substrate; forming a first inter-level dielectric layer on the substrate; forming a plurality of second inter-level dielectric layers on the first inter-level dielectric layer; forming a trench penetrating at least two of the second inter-level dielectric layers; and forming a first metal layer in the trench.

Abstract: An inductor module and a method for fabricating the same are disclosed. The inductor module includes a substrate, a first inter-level dielectric layer, a plurality of second inter-level dielectric layers, a trench, and a first metal layer. The first inter-level dielectric layer is disposed on the substrate. The second inter-level dielectric layers are sequentially stacked on the first inter-level dielectric layer. The trench is disposed to penetrate at least two of the second inter-level dielectric layers. The first metal layer is disposed in the trench. The first metal layer has a top side surface and a bottom side surface opposite to each other. The top side surface is coplanar with an upper surface of the trench in the second inter-level dielectric layers. The bottom side surface is coplanar with a bottom surface of the trench in the second inter-level dielectric layers.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region.

Abstract: An inductor module and a method for fabricating the same are disclosed. The inductor module includes a substrate, a first inter-level dielectric layer, a plurality of second inter-level dielectric layers, a trench, and a first metal layer. The first inter-level dielectric layer is disposed on the substrate. The second inter-level dielectric layers are sequentially stacked on the first inter-level dielectric layer. The trench is disposed to penetrate at least two of the second inter-level dielectric layers. The first metal layer is disposed in the trench. The first metal layer has a top side surface and a bottom side surface opposite to each other. The top side surface is coplanar with an upper surface of the trench in the second inter-level dielectric layers. The bottom side surface is coplanar with a bottom surface of the trench in the second inter-level dielectric layers.

Abstract: Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

Abstract: A multi-port inductor structure for use in semiconductor applications such as high-performance RF filters and amplifiers is provided. Embodiments of the present invention may provide 3 metallization layers and two via layers. The metallization layers and via layers may be substantially stacked on top of each other to conserve space. Each metallization layer comprises a ring pattern. In embodiments, the top two ring patterns include a plurality of concentric bands, forming a spiral pattern. The third (bottom) ring may include a broken ring pattern. In embodiments, the second (middle) ring may include one or more spans to facilitate connection to the inner bands of the second ring. The spans connect inner bands to an outer perimeter region of the second ring. Multiple tap points along the bands and spans allow multiple inductance values to be obtained from the structure.

Abstract: A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values.

Abstract: A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values.

Abstract: A multi-port inductor structure for use in semiconductor applications such as high-performance RF filters and amplifiers is provided. Embodiments of the present invention may provide 3 metallization layers and two via layers. The metallization layers and via layers may be substantially stacked on top of each other to conserve space. Each metallization layer comprises a ring pattern. In embodiments, the top two ring patterns include a plurality of concentric bands, forming a spiral pattern. The third (bottom) ring may include a broken ring pattern. In embodiments, the second (middle) ring may include one or more spans to facilitate connection to the inner bands of the second ring. The spans connect inner bands to an outer perimeter region of the second ring. Multiple tap points along the bands and spans allow multiple inductance values to be obtained from the structure.