Abstract: A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer and a sacrificial layer. The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics.

Abstract: An internet service node (ISN) enabling the provision of desired service policies to each subscriber. The desired service policies for each subscriber are provided as an input. The desired service policies are translated into processing rules. Each processing rule contains a classifier and associated action. A classifier generally identifies the application data flows to which the action may be applied to provide the desired service policies. The processing rules may be generated dynamically to implement the specified service policies for each subscriber. Each data bit group may be classified to associate with a subscriber and only the processing rules corresponding to the subscriber may be applied to the data bit group to provide the desired services.

Abstract: A method is provided of managing hardware triggered hotplug operations of one or more input/output (I/O) cards of a computer system. The method comprises receiving hardware triggers, each of which relates to a hotplug operation to be carried out on an I/O card associated with a card slot, placing the hardware triggers in a queue, and processing the queue of hardware triggers. The method further comprises processing one or more of said hardware triggers. This comprises analysing a hardware trigger to determine the card slot to which said hardware trigger relates, and consulting a hotplug operation policy to determine whether hotplug operations are enabled for said card slot. If hotplug operations are not enabled for said card slot, this further comprises ignoring said hardware trigger, and if hotplug operations are enabled for said card slot, this further comprise querying said slot to determine whether it contains a card.

Abstract: An internet service node (ISN) enabling the provision of desired service policies to each subscriber. The ISN may contain multiple processor groups, with each subscriber being assigned to a processor group. The assigned processor group may be configured with the processing rules, which provide the service policies desired, by a subscriber. A port may determine the specific processor group to which received data is to be forwarded. A content addressable memory with masks for individual locations may be implemented to quickly determines the processor group to which received data is to be assigned to. Due to the features of the present invention, an ISN may be able to serve a large number of subscribers efficiently. The ISN may be used at the edge of an access network.

Abstract: A system and method are disclosed for a segmented virtual machine. The segmented virtual machine includes a core VM and a shell VM associated with the core VM. The core VM is configured to perform VM internal execution functionality and the shell VM is configured to perform shell VM functions and communicate with the core VM.

Abstract: An internet service node (ISN) for sending unsolicited web pages only to users agreeing to receive unsolicited web page. An internet service provider (ISP) may charge lower rates to users agreeing to receive unsolicited web pages. For example, an ISP may send an unsolicited web page in response to the first web page request for a user. In general, a user may agree to receive different types of unsolicited web pages under different conditions. An ISN may monitor the data flows related to the user to determine whether any condition is satisfied; and a web server may be used to generate and send the corresponding unsolicited web page.

Abstract: A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding to the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: An internet service node (ISN) enabling the provision of desired service policies to each subscriber. The desired service policies for each subscriber are provided as an input. The desired service policies are translated into processing rules. Each processing rule contains a classifier and associated action. A classifier generally identifies the application data flows to which the action may be applied to provide the desired service policies. The processing rules may be generated dynamically to implement the specified service policies for each subscriber. Each data bit group may be classified to associate with a subscriber and only the processing rules corresponding to the subscriber may be applied to the data bit group to provide the desired services.

Abstract: A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.