Abstract: A method and a circuit of performing an analog to digital conversion in a charge redistribution circuit including a capacitor array of weighted capacitors and a transistor track switch for sampling an input signal into the capacitor array. A common mode voltage is stepped to a voltage sufficient to turn on the transistor track switch during a sampling phase. During the sampling phase, a top plate of each of the capacitors is coupled to the common mode voltage through the track switch while the bottom plate of each of the capacitors is coupled to an input to sample an input signal. During a conversion phase, the top plate of each of the capacitors is decoupled from the common mode voltage and the bottom plates of a selected one of the weighted capacitors is coupled to a first reference voltage, a weight of the selected one of the weighted capacitors proportional to the step in the common mode voltage.

Abstract: An analog multiplier or mixer that mixes a signal fc with a square wave local oscillator improves heterodyning operation of a circuit. In various square wave analog multiplier or mixer embodiments, heterodyning performance is improved in noise reduction, saturation performance, linearity, and other measures by adding a DC current path in parallel to a signal current path of the multiplier or mixer. The parasitic capacitances, noise, and nonlinearity problems in a heterodyning circuit are solved by adding a path to a square wave mixer for carrying the signal current and the DC current on different paths. An apparatus includes a circuit coupled between a first voltage reference and a second voltage reference. The circuit includes a first square wave oscillator branch and a second square wave oscillator branch. The first square wave oscillator branch is driven by a square wave oscillator signal and the second square wave oscillator branch is driven by an inverse of the square wave oscillator signal.

Abstract: A return path for use in a switched capacitor circuit includes an array of capacitors and a plurality of switches for selectively coupling voltages to capacitors. A set of latches selectively controls the plurality of switches during time periods partitioned into non-overlapping reset and set cycles. During a first such time period, a selected one of the capacitors is decoupled from a current voltage during the reset cycle and coupled to a selected reference voltage during the set cycle.

Abstract: A driver circuit 605 including a p-channel transistor 606 for driving an output from a supply rail at a positive supply voltage, p-channel transistor 606 disposed in an n-well. A detector 500 detects ramp down of the supply voltage below a preselected threshold voltage while a power reservoir 301 maintains a preselected well voltage of the n-well after the supply voltage ramps down below the preselected threshold.

Abstract: A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.

Abstract: A method of gain scaling in a charge redistribution analog to digital converter includes the step of segmenting a bit weighted capacitor array into a first segment having at least one capacitor representing a least significant bit and a second segment having at least one capacitor representing a most significant bit. During a sampling phase, an input signal is sampled onto the at least one capacitor of the second segment while the at least one capacitor of the first segment is coupled to a fixed voltage.

Abstract: A switched capacitor circuit includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array. A first plurality of switches selectively couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch samples the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node. A second plurality of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected onto the node.

Abstract: A receive path implementation for an intermediate frequency (IF) transceiver is disclosed that provides increased signal processing integrity and accuracy with an efficient and improved design. A complex filter for a bandpass delta-sigma analog-to-digital converter (ADC) provides efficient complex noise shaping with a combination of real and complex filters. An automatic gain control (AGC) amplifier provides a constant bandwidth and zero variation phase shift for all gain levels. Clock adjust circuitry provides a clock signal with a jitter-free edge and a high percentage duty cycle. A fixed-gain input amplifier provides a matched input impedance. A method for choosing design specifications provides improved anti-aliasing properties.

Abstract: An amplifier circuit having four variable impedance nodes is provided. The amplifier has split transconductance current paths. Each half of the amplifier has two such current paths and each current path has a node which may be either a high impedance or low impedance node. Connected between the two nodes is a transistor which is utilized in driving the nodes to their either high or low impedance state. The invention is particularly useful in a folded cascode amplifier used for driving loud speakers. However, the circuitry may also be used in other amplifiers or other applications. Further, the linearity of the amplifier's transfer curve may be improved to provide improved performance for high resistive loads. Thus, a class A-B amplifier is provided which can drive a wide range of resistive loads with varying linearity requirements. Moreover, the amplifier can be programmed to provide a high linearity region depending on the desired application.

Abstract: An amplifier circuit having four variable impedance nodes is provided. The amplifier has split transconductance current paths. Each half of the amplifier has two such current paths and each current path has a node which may be either a high impedance or low impedance node. Connected between the two nodes is a transistor which is utilized in driving the nodes to their either high or low impedance state. The invention is particularly useful in a folded cascode amplifier used for driving loud speakers. However, the circuitry may also be used in other amplifiers or other applications.