Patents by Inventor Shyam Sunder Raghunathan
Shyam Sunder Raghunathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240062829Abstract: Methods, systems, and devices for transient and stable state read operations of a memory device are described. A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Ugo Russo, Karan Banerjee, Shyam Sunder Raghunathan
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Patent number: 11762767Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or moreType: GrantFiled: April 22, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Giuseppina Puzzilli, Vamsi Pavan Rayaprolu, Ashutosh Malshe, James Fitzpatrick, Shyam Sunder Raghunathan, Violante Moschiano, Tecla Ghilardi
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Publication number: 20230197169Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.Type: ApplicationFiled: December 16, 2022Publication date: June 22, 2023Inventors: Violante Moschiano, Shyam Sunder Raghunathan, Walter Di Francesco
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Publication number: 20220415414Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.Type: ApplicationFiled: June 21, 2022Publication date: December 29, 2022Inventors: Violante Moschiano, Shyam Sunder Raghunathan, Haiou Che, Walter di Francesco
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Publication number: 20220342813Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or moreType: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Kishore Kumar Muchherla, Giuseppina Puzzilli, Vamsi Pavan Rayaprolu, Ashutosh Malshe, James Fitzpatrick, Shyam Sunder Raghunathan, Violante Moschiano, Tecla Ghilardi
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Patent number: 10658053Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: GrantFiled: September 26, 2017Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan
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Patent number: 10043574Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.Type: GrantFiled: February 28, 2018Date of Patent: August 7, 2018Assignee: Micron Technology, Inc.Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
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Publication number: 20180190347Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.Type: ApplicationFiled: February 28, 2018Publication date: July 5, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
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Publication number: 20180122487Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: ApplicationFiled: September 26, 2017Publication date: May 3, 2018Inventors: Shantanu R. RAJWADE, Pranav KALAVADE, Neal R. MIELKE, Krishna K. PARAT, Shyam Sunder RAGHUNATHAN
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Patent number: 9922704Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.Type: GrantFiled: June 22, 2016Date of Patent: March 20, 2018Assignee: Micron Technology, Inc.Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
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Patent number: 9792997Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: GrantFiled: June 15, 2016Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan
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Patent number: 9535777Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.Type: GrantFiled: November 22, 2013Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Pranav Kalavade, Feng Zhu, Shyam Sunder Raghunathan, Ravi H. Motwani
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Publication number: 20160372207Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: ApplicationFiled: June 15, 2016Publication date: December 22, 2016Inventors: Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan
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Publication number: 20160307622Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.Type: ApplicationFiled: June 22, 2016Publication date: October 20, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
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Patent number: 9418000Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.Type: GrantFiled: December 22, 2014Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Shyam Sunder Raghunathan, Iwen Chao, Xin Guo, Pranav Kalavade, Krishna K. Parat, Feng Zhu
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Patent number: 9418752Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: GrantFiled: March 27, 2014Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Shantanu R Rajwade, Pranav Kalavade, Neal R Mielke, Krishna K Parat, Shyam Sunder Raghunathan
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Patent number: 9396791Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.Type: GrantFiled: July 18, 2014Date of Patent: July 19, 2016Assignee: Micron Technology, Inc.Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
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Publication number: 20160180958Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.Type: ApplicationFiled: December 22, 2014Publication date: June 23, 2016Applicant: Intel CorporationInventors: SHYAM SUNDER RAGHUNATHAN, IWEN CHAO, XIN GUO, PRANAV KALAVADE, KRISHNA K. PARAT, FENG ZHU
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Patent number: 9245645Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.Type: GrantFiled: August 9, 2013Date of Patent: January 26, 2016Assignee: INTEL CORPORATIONInventors: Charan Srinivasan, Pranav Kalavade, Shyam Sunder Raghunathan, Krishna K. Parat
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Publication number: 20160019949Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.Type: ApplicationFiled: July 18, 2014Publication date: January 21, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan