Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.

Abstract: In one or more embodiments, one or more methods, processes, and/or systems may receive quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU); may configure one or more registers of the memory controller with a range of addresses associated; may determine performance data based at least on one or more of an average number of transactions completed, an average number of cycles utilized by the transactions, and an average number of credits in a flow control between the memory controller and a first memory medium coupled to the memory controller; may determine that the performance data does not comply with the QoS configuration information; and if the performance data indicates that the information storage and retrieval of the device is congested, may remap the IOMMU to point to DMA buffers of a second memory medium.

Abstract: In one or more embodiments, one or more methods, processes, and/or systems may receive quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU); may configure one or more registers of the memory controller with a range of addresses associated; may determine performance data based at least on one or more of an average number of transactions completed, an average number of cycles utilized by the transactions, and an average number of credits in a flow control between the memory controller and a first memory medium coupled to the memory controller; may determine that the performance data does not comply with the QoS configuration information; and if the performance data indicates that the information storage and retrieval of the device is congested, may remap the IOMMU to point to DMA buffers of a second memory medium.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure an input/output memory management unit; may receive, from a device associated with an information handling system, a request for an allocation of storage of a memory medium of the information handling system; may allocate the storage of the memory medium without an interaction with a processor of the information handling system and without an interaction with an operating system executed by the processor; may add a table entry, associated with the allocation of storage of the memory medium, to a page table; may provide update information to the operating system; may provide a success response to the device; may store first data from the device; and may provide second data to the device.