Patents by Inventor Shyan-Liang Chou
Shyan-Liang Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10475925Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.Type: GrantFiled: May 21, 2018Date of Patent: November 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Hsu, Hsin-Che Huang, Shyan-Liang Chou, Hung-Lin Shih
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Publication number: 20180277679Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.Type: ApplicationFiled: May 21, 2018Publication date: September 27, 2018Inventors: Wei-Lun Hsu, Hsin-Che Huang, Shyan-Liang Chou, Hung-Lin Shih
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Patent number: 10008599Abstract: A complementary metal oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate with a first device region and a second device region formed thereon. A first isolation structure is formed in the first device region, and includes a first trench filled with a first material. A second isolation structure is formed in the second device region and includes a second trench filled with a second material. The first material and the second material have different stresses. A first gate structure is disposed atop the first material and completely covering the first trench. A second gate structure is disposed atop the second material and completely covering the second trench.Type: GrantFiled: March 1, 2017Date of Patent: June 26, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Hsu, Hsin-Che Huang, Shyan-Liang Chou, Hung-Lin Shih
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Patent number: 9117904Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.Type: GrantFiled: January 28, 2015Date of Patent: August 25, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Publication number: 20150137197Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Patent number: 8975673Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.Type: GrantFiled: April 16, 2012Date of Patent: March 10, 2015Assignee: United Microelectronics Corp.Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Patent number: 8692334Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: GrantFiled: July 24, 2013Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Publication number: 20130307084Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Publication number: 20130270613Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.Type: ApplicationFiled: April 16, 2012Publication date: October 17, 2013Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
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Publication number: 20130241002Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Patent number: 8524556Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: GrantFiled: March 14, 2012Date of Patent: September 3, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao