Patents by Inventor Shyh-Chyi Yang

Shyh-Chyi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device capable of releasing stress voltage
    Patent number: 10692568
    Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 23, 2020
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Shyh-Chyi Yang, Wei-Chiang Shih
  • MEMORY DEVICE CAPABLE OF RELIEVING VOLTAGE STRESS
    Publication number: 20190088311
    Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 21, 2019
    Inventors: Shyh-Chyi YANG, Wei-Chiang SHIH
  • Disturb-free static random access memory cell
    Patent number: 8259510
    Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: September 4, 2012
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Hao-I Yang, Jihi-Yu Lin, Shyh-Chyi Yang, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Kun-Ti Lee, Hung-Yu Li
  • DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
    Publication number: 20110128796
    Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.
    Type: Application
    Filed: May 3, 2010
    Publication date: June 2, 2011
    Inventors: Ching-Te Chuang, Hao-I Yang, Jihi-Yu Lin, Shyh-Chyi Yang, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Kun-Ti Lee, Hung-Yu Li