Patents by Inventor Shyh-Horng Lin

Shyh-Horng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9696377
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 4, 2017
    Assignee: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
  • Patent number: 9682062
    Abstract: The disclosure provides a pharmaceutical composition for inhibiting angiogenesis, including an effective amount of an extract of Juniperus chinensis or an effective amount of a lignan as an effective ingredient. The pharmaceutical composition may further include a pharmaceutically acceptable carrier or salt. The disclosure also provides a method for inhibiting angiogenesis, including administering an effective amount of an extract of Juniperus chinensis or an effective amount of a lignan as an effective ingredient for inhibiting angiogenesis to a subject in need thereof.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: June 20, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Horng Pan, Hsin-Jan Yao, Mei-Wei Lin, I-Huang Lu, Hsin-Chieh Wu, Hsiang-Wen Tseng, Ching-Huai Ko, Chun-Chung Wang, Zong-Keng Kuo, Shyh-Horng Lin, Yi-Cheng Cheng, Tien-Soung Tong
  • Patent number: 9474735
    Abstract: A pharmaceutical preparation containing polymeric compounds as shown in the specification. This preparation can be used to improve liver function and treat liver disease, and promoting liver tissue regeneration.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 25, 2016
    Assignee: Industrial Technology Research Institute (ITRI)
    Inventors: Shau-Feng Chang, Chun-Hsien Ma, Kuo-Yi Yang, Chien-Tung Lin, Shyh-Horng Lin, Kai-Wen Huang
  • Publication number: 20160008319
    Abstract: The disclosure provides a pharmaceutical composition for inhibiting angiogenesis, including an effective amount of a lignan as an effective ingredient. The pharmaceutical composition may further include a pharmaceutically acceptable carrier or salt. The disclosure also provides a method for inhibiting angiogenesis, including administering an effective amount of a lignan as an effective ingredient for inhibiting angiogenesis to a subject in need thereof.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 14, 2016
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Horng PAN, Hsin-Jan YAO, Mei-Wei LIN, I-Huang LU, Hsin-Chieh WU, Hsiang-Wen TSENG, Ching-Huai KO, Chun-Chung WANG, Zong-Keng KUO, Shyh-Horng LIN, Yi-Cheng CHENG, Tien-Soung TONG
  • Publication number: 20150133539
    Abstract: A pharmaceutical preparation containing polymeric compounds as shown in the specification. This preparation can be used to improve liver function and treat liver disease, and promoting liver tissue regeneration.
    Type: Application
    Filed: December 17, 2014
    Publication date: May 14, 2015
    Inventors: Shau-Feng Chang, Chun-Hsien Ma, Kuo-Yi Yang, Chien-Tung Lin, Shyh-Horng Lin, Kai-Wen Huang
  • Publication number: 20140170250
    Abstract: The disclosure provides a pharmaceutical composition for inhibiting angiogenesis, including an effective amount of an extract of Juniperus chinensis or an effective amount of a lignan as an effective ingredient. The pharmaceutical composition may further include a pharmaceutically acceptable carrier or salt. The disclosure also provides a method for inhibiting angiogenesis, including administering an effective amount of an extract of Juniperus chinensis or an effective amount of a lignan as an effective ingredient for inhibiting angiogenesis to a subject in need thereof.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 19, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Horng PAN, Hsin-Jan YAO, Mei-Wei LIN, I-Huang LU, Hsin-Chieh WU, Hsiang-Wen TSENG, Ching-Huai KO, Chun-Chung WANG, Zong-Keng KUO, Shyh-Horng LIN, Yi-Cheng CHENG, Tien-Soung TONG
  • Patent number: 8543950
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: September 24, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang
  • Publication number: 20110158933
    Abstract: A pharmaceutical preparation containing polymeric compounds as shown in the specification. This preparation can be used to improve liver function and treat liver disease, and promoting liver tissue regeneration.
    Type: Application
    Filed: October 20, 2010
    Publication date: June 30, 2011
    Applicant: Industrial Technology research Institute (ITRI)
    Inventors: Shau-Feng Chang, Chun-Hsien Ma, Kuo-Yi Yang, Chien-Tung Lin, Shyh-Horng Lin, Kai-Wen Huang
  • Patent number: 7721173
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: May 18, 2010
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
  • Publication number: 20090235132
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Application
    Filed: May 20, 2009
    Publication date: September 17, 2009
    Applicant: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
  • Patent number: 7552373
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: June 23, 2009
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
  • Patent number: 7512851
    Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: March 31, 2009
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin (Sam) Wang, Ming-Tung Chang
  • Publication number: 20090037786
    Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.
    Type: Application
    Filed: September 30, 2008
    Publication date: February 5, 2009
    Inventors: Laung-Terng Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
  • Publication number: 20080276141
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 6, 2008
    Inventors: Laung-Terng(L.-T.) Wang, Xiaoqing Wen, Shyh-Horng Lin, Khader S. Abdel-Hafez
  • Patent number: 7444567
    Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: October 28, 2008
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
  • Patent number: 7412672
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: August 12, 2008
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Xiaoqing Wen, Shyh-Horng Lin, Khader S. Abdel-Hafez
  • Patent number: 7331032
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: February 12, 2008
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L. -T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Xiaoqing Wen, Shih-Chia Kao, Shyh-Horng Lin, Hsin-Po Wang
  • Patent number: 7228479
    Abstract: An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: June 5, 2007
    Assignee: Syntest Technologies, Inc.
    Inventors: Chauchin Su, Shyh-Horng Lin, Laung-Terng (L.-T.) Wang
  • Patent number: 7191373
    Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: March 13, 2007
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu
  • Publication number: 20060059395
    Abstract: An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 16, 2006
    Inventors: Chauchin Su, Shyh-Horng Lin, Laung-Terng Wang