Patents by Inventor Shyh-Horng Yang
Shyh-Horng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105851Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first well region and a second well region in a substrate. The method includes forming a third well region in the substrate and between the first well region and the second well region. The method includes forming a deep well region in the substrate and under the first well region and the third well region. The method includes partially removing the substrate to form a first fin, a second fin, and a third fin in the first well region, the second well region, and the third well region respectively. The method includes forming a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure in the first recess, the second recess, and the third recess respectively.Type: ApplicationFiled: January 12, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiefeng Jeff LIN, Chen-Hua TSAI, Shyh-Horng YANG
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Patent number: 11489054Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: GrantFiled: November 16, 2020Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 10978355Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.Type: GrantFiled: May 22, 2018Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20210083063Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: November 16, 2020Publication date: March 18, 2021Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 10840346Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: GrantFiled: September 12, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20200006505Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 10516024Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: GrantFiled: April 3, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20180269112Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20180226479Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 10014223Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.Type: GrantFiled: October 19, 2015Date of Patent: July 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9941368Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: GrantFiled: December 1, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yonag-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9634104Abstract: A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.Type: GrantFiled: May 13, 2015Date of Patent: April 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Donald Y. Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20170084709Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: December 1, 2016Publication date: March 23, 2017Inventors: Yonag-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9514991Abstract: A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers.Type: GrantFiled: October 13, 2015Date of Patent: December 6, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9515167Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: GrantFiled: September 25, 2015Date of Patent: December 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yonag-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9431397Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.Type: GrantFiled: February 16, 2015Date of Patent: August 30, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9317647Abstract: A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.Type: GrantFiled: March 31, 2014Date of Patent: April 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shyh-Horng Yang, Chung-Kai Lin, Chung-Hsing Wang, Kuo-Nan Yang, Shou-En Liu, Jhong-Sheng Wang, Tan-Li Chou
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Publication number: 20160043002Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.Type: ApplicationFiled: October 19, 2015Publication date: February 11, 2016Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20160035625Abstract: A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20160013297Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: September 25, 2015Publication date: January 14, 2016Inventors: Yonag-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang