Patents by Inventor Shyh-Ing Wu
Shyh-Ing Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7727878Abstract: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.Type: GrantFiled: December 28, 2006Date of Patent: June 1, 2010Assignee: Advanced Semiconductor Engineering Inc.Inventors: Cheng-Hsueh Su, Hsing-Fu Lu, Tsung-Chieh Ho, Shyh-Ing Wu
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Patent number: 7651937Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.Type: GrantFiled: August 11, 2006Date of Patent: January 26, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
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Patent number: 7518241Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.Type: GrantFiled: August 31, 2006Date of Patent: April 14, 2009Assignee: Advanced Semiconductor Engineering Inc.Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
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Publication number: 20070232052Abstract: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.Type: ApplicationFiled: December 28, 2006Publication date: October 4, 2007Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Cheng-Hsueh Su, Hsing-Fu Lu, Tsung-Chieh Ho, Shyh-Ing Wu
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Publication number: 20070108612Abstract: A chip structure and a manufacturing method of the same. The chip structure includes a base, a pad, a first passivation layer, a second passivation layer and a bump. The pad is formed on the base. The first passivation layer is formed on the base exposing the pad. The second passivation layer formed on the first passivation layer has a passivation layer opening which is positioned above the pad. The bump is formed on the pad, and a part of the bump is disposed inside the passivation layer opening. The width at the bottom of the passivation layer opening is larger than the width at the top of the passivation layer opening, such that the bump is firmly fixed by the second protection layer.Type: ApplicationFiled: August 29, 2006Publication date: May 17, 2007Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
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Publication number: 20070049001Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.Type: ApplicationFiled: August 11, 2006Publication date: March 1, 2007Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
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Publication number: 20070045848Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.Type: ApplicationFiled: August 31, 2006Publication date: March 1, 2007Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
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Publication number: 20060097392Abstract: A kind of wafer structure including a plurality of chip, first passivation layer, a plurality of buffer pad, second passivation layer, and a plurality of bump. Each chip has an active surface, on which a plurality of bonding pad are disposed. The first passivation layer is disposed on the active surface of the chips. First passivation layer has a plurality of first openings, each of which exposes a bonding pad. The buffer pads are disposed on the first openings and the surrounding first passivation layer. The buffer pads are electrically connected with bonding pad. The second passivation layer is disposed on the first passivation layer. The second passivation layer has a plurality of second openings, each of which exposes a buffer pad. The bumps are disposed inside the second openings and electrically connected with buffer pads.Type: ApplicationFiled: November 3, 2005Publication date: May 11, 2006Inventor: Shyh-Ing Wu
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Patent number: 6918178Abstract: An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.Type: GrantFiled: January 17, 2003Date of Patent: July 19, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shin-Hua Chao, Shyh-Ing Wu, Kuan-Neng Liao, Gin-Nan Yeh
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Publication number: 20040124171Abstract: A bump-forming process is provided. An adhesion layer is formed on an active surface of a wafer. A barrier layer and a wettable layer are sequentially formed over the adhesion layer. A portion of the wettable layer and a portion of the barrier layer are removed and then a patterned mask layer is formed over the adhesion layer. The mask layer has a plurality of openings that at least exposes the wettable layer. A printing process is performed to deposit solder paste into the openings. Thereafter, a reflow process is carried out so that the solder paste inside the openings is transformed into bumps. The mask layer is removed, followed by removing the adhesion layer outside the residual wettable layer and the residual barrier layer.Type: ApplicationFiled: September 24, 2003Publication date: July 1, 2004Inventor: Shyh-Ing Wu
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Patent number: 6692581Abstract: A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.Type: GrantFiled: February 20, 2003Date of Patent: February 17, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Ching-Fu Horng, Shih-Kuang Chen, Shyh-Ing Wu, Chun-Hung Lin, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Publication number: 20030164204Abstract: A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.Type: ApplicationFiled: February 20, 2003Publication date: September 4, 2003Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Ching-Fu Horng, Shih-Kuang Chen, Shyh-Ing Wu, Chun-Hung Lin, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Publication number: 20030106212Abstract: An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.Type: ApplicationFiled: January 17, 2003Publication date: June 12, 2003Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shin-Hua Chao, Shyh-Ing Wu, Kuan-Neng Liao, Gin-Nan Yeh
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Patent number: 6429049Abstract: A laser method for forming vias comprises: providing a heat sink; locally oxidizing a surface of the heat sink into a copper oxide film; bonding a substrate onto the heat sink at the copper oxide layer locations, wherein the substrate comprises at least a patterned trace layer and an insulating layer to which is bonded the heat sink, the insulating layer comprising a plurality of through holes that expose the portions of the copper oxide film; removing the copper oxide exposed through the through holes by laser beam; disposing a plurality of solder balls respectively in the through holes; and reflowing the solder balls to form a plurality of vias.Type: GrantFiled: June 5, 2001Date of Patent: August 6, 2002Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Chi Lee, Jaw-Shiun Hsieh, Yao-Hsin Feng, Shyh-Ing Wu, Kuan-Neng Liao, Chin-Pei Tien
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Patent number: 6355499Abstract: A method of making a ball grid array package comprises the steps of: (a) providing a film having an opening defined therein; (b) placing the film on a substrate; (c) attaching a semiconductor chip onto the substrate such that the semiconductor chip is positioned in the opening of the film; (d) electrically coupling the semiconductor chip to the substrate; (e) providing a molding die having a runner, a gate and a molding cavity defined therein, wherein the runner is connected to the molding cavity through the gate; (f) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the molding cavity wherein the edges of the molding cavity fit entirely within the opening of the film and the edges of the runners and the gates are entirely positioned against the film; (g) transferring a hardenable molding compound into the molding cavity; (h) hardening the molding compound; (i) unclamping and opening the molding die; and (j) simultaneously removing the film and degating.Type: GrantFiled: July 6, 2000Date of Patent: March 12, 2002Assignee: Advanced Semiconductor Engineering. Inc.Inventors: Shyh-Ing Wu, Shin Hua Chao, Yao Shin Fang
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Patent number: 6252309Abstract: A packaged semi-conductor substrate includes a package encapsulant pouring area, a layout provided on the substrate, a layer of solder mask deposited on the layout, and a film provided on the solder mask. When the package encapsulant is pouted into the package encapsulant pouring area, the package encapsulant is isolated from the solder mask by the film. An adhering force between the film and the package encapsulant is greater than an adhering force between the film and the mask such that the film is degated along with the package encapsulant in the pouring channel during a degating procedure of the pouring channel after a pouring procedure of the package encapsulant. Thus, the film and the package encapsulant are not residual on the substrate.Type: GrantFiled: January 8, 1999Date of Patent: June 26, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Wu-Chang Wang, Yung-I Yeh, Kun-Ching Chen, Shyh-Ing Wu
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Patent number: 5982625Abstract: A semiconductor packaging device includes a printed circuit board substrate, a mold gate formed on a periphery of the printed circuit board substrate through which a package encapsulant is poured to enclose electric elements mounted on a side of the printed circuit board, and a layer of non-metallic material covered on the side of the printed circuit board substrate in the mold gate area. The package encapsulant, after hardened, is bonded with the layer of non-metallic material, and the bonded package encapsulant/the layer of non-metallic material is degatable from the mold gate.Type: GrantFiled: March 19, 1998Date of Patent: November 9, 1999Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kun-Ching Chen, Tao-Yu Chen, Yung-I Yeh, Wu-Chang Wang, Chun-Che Lee, Chun-Hsiung Huang, Shyh-Ing Wu