Abstract: A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first groove and the first connection slot. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove. The connection metal layer covers the under bump metallurgy layer to form a third groove, wherein the under bump metallurgy layer covers a first coverage area of the first polymer block and a second coverage area of the second polymer block and reveals a first exposure area of the first polymer block and a second exposure area of the second polymer block.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first groove and the first connection slot. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove. The connection metal layer covers the under bump metallurgy layer to form a third groove, wherein the under bump metallurgy layer covers a first coverage area of the first polymer block and a second coverage area of the second polymer block and reveals a first exposure area of the first polymer block and a second exposure area of the second polymer block.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.

Abstract: A method for fabricating a mask (or reticle) to improve the mask ESD immunity is provided. A substrate having an upper surface is substantially transparent to a selected radiation. A light sensitive layer is formed over the substrate. The light sensitive layer is patterned and etched to form a pattern of openings in the light sensitive layer. The substrate is etched according to the pattern of openings in the light sensitive layer. The light sensitive layer is stripped. An opaque layer is then deposited on the upper surface and in the openings of the patterned substrate. The substrate is planarized by removing excess opaque layer from over the upper surface of the substrate. A pellicle is then mounted outstretched on the upper surface of the substrate.

Abstract: A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.