Patents by Inventor Shyoichi Miyazawa

Shyoichi Miyazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5559645
    Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: September 24, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shyoichi Miyazawa, Ryutaro Horita, Kenichi Hase, Satoshi Kawamura, Shinichi Kojima, Toshiyuki Iseki
  • Patent number: 5402274
    Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
    Type: Grant
    Filed: October 21, 1992
    Date of Patent: March 28, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shyoichi Miyazawa, Ryutaro Horita, Kenichi Hase, Satoshi Kawamura, Shinichi Kojima, Toshiyuki Iseki
  • Patent number: 5187615
    Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
    Type: Grant
    Filed: July 22, 1991
    Date of Patent: February 16, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shyoichi Miyazawa, Ryutaro Horita, Kenichi Hase, Satoshi Kawamura, Shinichi Kojima, Toshiyuki Iseki
  • Patent number: 5062011
    Abstract: When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: October 29, 1991
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Kenichi Hase, Shyoichi Miyazawa, Ryutaro Horita, Shinichi Kojima, Akira Uragami, Takashi Watanabe, Yoshinori Yoshino
  • Patent number: 4809091
    Abstract: A disk drive system includes a magnetic disk apparatus which accurately positions read/write heads for reading data from and writing data on tracks on the data surface of a rotary disk on a predetermined track on the disk on the basis of servo data written in the servo area formed on the data surface, and a disk controller which controls the mode of operation of the disk apparatus. Index signals respectively indicating the start and end of the servo area are generated on the basis of the result of detection of the angular phase of the disk. The mode of operation of the magnetic disk apparatus is determined on the basis of a write control signal provided by the disk controller. The index signals respectively indicating the start and end of the servo area are sent to the disk controller when the mode of operation is track format write mode, while the index signal indicating the end of the servo area is sent to the disk controller when the mode of operation is other than the track format write mode.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: February 28, 1989
    Assignees: Hitachi, Ltd., Tokico Ltd.
    Inventors: Shyoichi Miyazawa, Satoshi Kawamura, Shoichiro Tohyama, Akira Ishibashi, Kazutoshi Kato, Junichi Ideda
  • Patent number: 4523276
    Abstract: An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: June 11, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Maejima, Ikuro Masuda, Hidekazu Matsumoto, Shyoichi Miyazawa