Patents by Inventor Shyue Seng (Jason) Tan
Shyue Seng (Jason) Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11251095Abstract: An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog high gain transistor includes a double well, which includes the well implants of the low voltage (LV) and intermediate voltage (IV) transistors. In addition, the analog high gain transistor includes light doped extension regions of IV transistor and a thin gate dielectric of the LV transistor.Type: GrantFiled: June 13, 2016Date of Patent: February 15, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Yuan Sun, Shyue Seng Jason Tan
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Patent number: 10096602Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.Type: GrantFiled: March 15, 2017Date of Patent: October 9, 2018Assignee: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.Inventors: Shyue Seng Jason Tan, Kiok Boone Elgin Quek
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Publication number: 20180269209Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.Type: ApplicationFiled: March 15, 2017Publication date: September 20, 2018Inventors: Shyue Seng Jason TAN, Kiok Boone Elgin QUEK
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Publication number: 20170358501Abstract: An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog high gain transistor includes a double well, which includes the well implants of the low voltage (LV) and intermediate voltage (IV) transistors. In addition, the analog high gain transistor includes light doped extension regions of IV transistor and a thin gate dielectric of the LV transistor.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventors: Yuan SUN, Shyue Seng Jason TAN
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Patent number: 9818867Abstract: Non-volatile (NV) Multi-time programmable (MTP) memory cells are presented. The memory cell includes a substrate and first and second wells in the substrate. The memory cell includes first transistor having a select gate, second transistor having a floating gate adjacent to one another and on the second well, and third transistor having a control gate on the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and second wells. The transistors include first and second diffusion regions disposed adjacent to sides of the gates. The first and second diffusion regions include base lightly doped drain (LDD) and halo regions. One of the first and second diffusion regions of one of the second and third transistors includes second LDD and halo regions having higher dopant concentrations than the base LDD and halo regions.Type: GrantFiled: October 24, 2014Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shyue Seng Jason Tan, Yuan Sun, Eng Huat Toh, Ying Keung Leung, Kiok Boone Elgin Quek
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Publication number: 20160268387Abstract: A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.Type: ApplicationFiled: March 10, 2015Publication date: September 15, 2016Inventors: Eng Huat TOH, Shyue Seng (Jason) TAN
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Patent number: 9312268Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.Type: GrantFiled: September 2, 2014Date of Patent: April 12, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Eng Huat Toh, Shyue Seng Jason Tan, Elgin Kiok Boone Quek, Danny Shum
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Publication number: 20160093630Abstract: A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.Type: ApplicationFiled: December 10, 2015Publication date: March 31, 2016Inventors: Shyue Seng (Jason) TAN, Eng Huat TOH, Elgin QUEK
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Publication number: 20160064398Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.Type: ApplicationFiled: September 2, 2014Publication date: March 3, 2016Inventors: Eng Huat Toh, Shyue Seng Jason Tan, Elgin Kiok Boone Quek, Danny Shum
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Patent number: 9064803Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.Type: GrantFiled: July 25, 2011Date of Patent: June 23, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Eng Huat Toh, Shyue Seng (Jason) Tan, Elgin Quek
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Patent number: 8999828Abstract: A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.Type: GrantFiled: August 3, 2011Date of Patent: April 7, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Eng Huat Toh, Shyue Seng (Jason) Tan
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Publication number: 20150054043Abstract: Non-volatile (NV) Multi-time programmable (MTP) memory cells are presented. The memory cell includes a substrate and first and second wells in the substrate. The memory cell includes first transistor having a select gate, second transistor having a floating gate adjacent to one another and on the second well, and third transistor having a control gate on the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and second wells. The transistors include first and second diffusion regions disposed adjacent to sides of the gates. The first and second diffusion regions include base lightly doped drain (LDD) and halo regions. One of the first and second diffusion regions of one of the second and third transistors includes second LDD and halo regions having higher dopant concentrations than the base LDD and halo regions.Type: ApplicationFiled: October 24, 2014Publication date: February 26, 2015Inventors: Shyue Seng, Jason TAN, Yuan SUN, Eng Huat TOH, Ying Keung LEUNG, Kiok Boone, Elgin QUEK
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Patent number: 8803122Abstract: Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.Type: GrantFiled: July 31, 2012Date of Patent: August 12, 2014Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh
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Patent number: 8536558Abstract: Resistive random-access memory (RRAM) structures are formed with ultra-thin RRAM-functional layers, thereby improving memory margins. Embodiments include forming an interlayer dielectric (ILD) over a bottom electrode, forming a sacrificial layer over the ILD, removing a portion of the ILD and a portion of the sacrificial layer vertically contiguous with the portion of the ILD, forming a cell area, forming a metal layer within the cell area, forming an interlayer dielectric structure above or surrounded by and protruding above the metal layer, a top surface of the interlayer dielectric structure being coplanar with a top surface of the sacrificial layer, removing the sacrificial layer, forming a memory layer on the ILD and/or on side surfaces of the interlayer dielectric structure, and forming a dielectric layer surrounding at least a portion of the interlayer dielectric structure.Type: GrantFiled: July 31, 2012Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh, Elgin Quek
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Publication number: 20130037877Abstract: A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh, Elgin Quek
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Publication number: 20130032869Abstract: A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Eng Huat Toh, Shyue Seng (Jason) Tan
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Publication number: 20130026552Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Inventors: Eng Huat Toh, Shyue Seng (Jason) Tan, Elgin Quek
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Publication number: 20120292735Abstract: The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.Type: ApplicationFiled: May 20, 2011Publication date: November 22, 2012Applicant: GLOBALFOUNDRIES Singapore Pte.Ltd.Inventors: Shyue Seng (Jason) Tan, Ying Keung Leung, Elgin Quek
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Publication number: 20120217467Abstract: A Fin FET SONOS device is formed with a full buried channel. Embodiments include forming p-type silicon fins protruding from a first oxide layer, an n-type silicon layer over exposed surfaces of the fins, a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer, and a polysilicon layer on the third oxide layer. Embodiments include etching a silicon layer to form the fins and forming the oxide on the silicon layer. Different embodiments include: etching a silicon layer on a BOX layer to form the fins; forming the fins with a rounded top surface; and forming nano-wires surrounded by an n-type silicon layer, a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon layer over a BOX layer.Type: ApplicationFiled: February 24, 2011Publication date: August 30, 2012Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh, Elgin Quek