Abstract: A method of multi-symbol channel estimation for estimating channel response to a plurality of transmission symbols within an observation window transmitted through a time-varying channel in a multi-carrier modulation system is provided. The method is to be implemented using a channel estimation device, and includes the steps of: obtaining a window pilot receive vector according to a part of elements of each of receive symbols corresponding to pilots in a corresponding one of the transmission symbols; computing a window pilot channel trans form matrix based upon the pilots in the transmission symbols; computing an estimated value of a polynomial coefficient vector based upon the window pilot receive vector and the window pilot channel transform matrix; and for each of the transmission symbols, computing a plurality of estimated values of channel response associated with possible transmission paths in the time-varying channel according to the estimated value of the polynomial coefficient vector.

Abstract: A method of multi-symbol channel estimation for estimating channel response to a plurality of transmission symbols within an observation window transmitted through a time-varying channel in a multi-carrier modulation system is provided. The method is to be implemented using a channel estimation device, and includes the steps of: obtaining a window pilot receive vector according to a part of elements of each of receive symbols corresponding to pilots in a corresponding one of the transmission symbols; computing a window pilot channel trans form matrix based upon the pilots in the transmission symbols; computing an estimated value of a polynomial coefficient vector based upon the window pilot receive vector and the window pilot channel transform matrix; and for each of the transmission symbols, computing a plurality of estimated values of channel response associated with possible transmission paths in the time-varying channel according to the estimated value of the polynomial coefficient vector.

Abstract: A signal transmitting method, a signal receiving method, and a signal receiving device are adapted to an OFDM system. In the signal transmitting method and signal receiving method, double asymmetric training symbols are used for performing time-varying channel response estimation. In the transmitting method, asymmetric pilot sub-carriers are added in data sub-carriers to form a plurality of first and second training symbols. The pilot symbols in the first and second training symbols are asymmetrically configured. In the receiving method, a channel response corresponding to each pilot sub-carrier is estimated by using two adjacent asymmetric pilot symbols. The received data sub-carrier is then restored through the channel response. Through the signal transmitting method and signal receiving method, even in a transmitter or a receiver moving at a high speed, more bandwidths can be used to transfer data, and contents of the transferred data can be correctly estimated.

Abstract: A signal transmitting method, a signal receiving method, and a signal receiving device are adapted to an OFDM system. In the signal transmitting method and signal receiving method, double asymmetric training symbols are used for performing time-varying channel response estimation. In the transmitting method, asymmetric pilot sub-carriers are added in data sub-carriers to form a plurality of first and second training symbols. The pilot symbols in the first and second training symbols are asymmetrically configured. In the receiving method, a channel response corresponding to each pilot sub-carrier is estimated by using two adjacent asymmetric pilot symbols. The received data sub-carrier is then restored through the channel response. Through the signal transmitting method and signal receiving method, even in a transmitter or a receiver moving at a high speed, more bandwidths can be used to transfer data, and contents of the transferred data can be correctly estimated.

Abstract: An arithmetic unit which performs all basic arithmetic operations in a finite field GF(2m) and includes an arithmetic processor, an arithmetic logic unit and a control unit is disclosed. The arithmetic unit of the present invention is structured with a low circuit complexity, so that an error-correcting decoder applying this calculating processor can be greatly simplified.

Abstract: Circuits, designed on the basis of power-sum circuits, for performing exponentiation (B.sup.N) and inversion (B.sup.-1) computations in finite field GF(2.sup.m) where B is an arbitrary elements of GF(2.sup.m), are presented . The circuit for performing inversion (B.sup.-1) computations can be deemed another version of the circuit performing exponentiation (B.sup.N) computations. With pipeline architecture and on the basis of power-sum circuits, these circuits are featured by simplicity, regularity, and broader application (applicable to an arbitrary element of the finite field).

Abstract: Circuits, designed on the basis of power-sum circuits and inversion (B.sup.-1) computation structure where B is an arbitrary elements of GF(2.sup.m), for performing division computations in finite field GF(2.sup.m), are presented. The circuit can be deemed an extension of the circuit performing inversion (B.sup.-1) computations. With pipeline architecture and on the basis of power-sum circuits, the circuit is featured by simplicity, regularity, and broader application (applicable to arbitrary elements of the finite field) GF(2.sup.m).

Abstract: A cellular-array power-sum circuit designed to perform AB.sup.2 +C computations in the finite field GF(2.sup.m) is presented, where A, B, and C are arbitrary elements of GF(2.sup.m). This new circuit is made up of m.sup.2 identical cells each consisting of an AND logic unit and an exclusive-OR logic unit. The AND logic unit may be configured to comprise three 2-input AND gates, and the exclusive-OR logic unit may be configured to comprise one 4-input XOR gate. The presented cellular-array power-sum circuit has a computation time of 2m gate delays. It is this power-sum circuit that provides basis for using circuits of pipeline architectures to compute exponentiations, inversions, and divisions in GF(2.sup.m).

Abstract: A decoder is utilized for the correction of bit errors occurred in BCH (Bose-Chaudhuri-Hocquenghem) codes. The decoder first calculates the syndromes of a received word. The syndrome values form a first group of syndrome matrices whose determinant values are used for determining the weight of the error pattern of the received word. Subsequently, during each error trial testing, the bits constituting the received word are cyclically shifted and a predetermined bit is inverted to form a new word to see how the corresponding weight of the error pattern is changed thereby. If the weight is increased, the predetermined bit before being inverted is a correct one; otherwise if decreased the same is an erroneous one and thus correcting action is undertaken. The weight of the error pattern of a word is determined by the zeroness of the determinants of a plurality of matrices formed by the syndrome values thereof.

Abstract: A decoder is utilized at the receiving end of a digital communication system for correcting symbol errors occurred in a received digital information which has been encoded into a group of Reed-Solomon codewords. The method used in the decoder follows a modified step-by-step decoding procedure. The decoder first calculates the syndromes of a received word. The syndromes form a first group of matrices whose determinant values are used for determining the weight of the error pattern of the received word. Subsequently, each of the symbols constituting the received word is altered to see how the corresponding weight of the error pattern of the altered word is changed thereby. If the weight is increased, the symbol being altered is a correct one; otherwise if decreased the symbol being altered is an erroneous one and thus correcting action is undertaken.