Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

Abstract: An image sensor with an enlarged outward appearance of a microlens and a method for fabricating the same are provided. The image sensor includes: a plurality of microlenses formed on a semiconductor substrate with a certain spacing distance; and a protection layer formed over the microlenses, wherein the protection layer includes a first oxide layer which is formed by a plasma enhanced chemical vapor deposition (PECVD) method and a second oxide layer which is formed by a spin on glass (SOG) method over the first oxide layer to maintain sufficient step coverage over chasms between the microlenses.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: Disclosed is a method of forming a copper wiring in a semiconductor device. A copper barrier metal layer and a copper seed layer are sequentially formed along the surface of an interlayer insulating film including damascene patterns. In a state that a wafer is then loaded onto an electrical plating apparatus in which a copper plating solution is filled and a negative (?) power supply is also applied to the wafer, copper is plated so that the damascene patterns are sufficiently filled, thereby forming a copper layer. Next, the copper layer is polished in the plating solution by means of the electro-polishing process by changing the negative (?) power supply to the positive (+) power supply. Due to this, the surface of the copper layer is flat over the entire wafer. Thereafter, a chemical mechanical polishing process is performed until the surface of the interlayer insulating film is exposed, thereby forming copper wirings within the damascene patterns.

Abstract: An image sensor with an enlarged outward appearance of a microlens and a method for fabricating the same are provided. The image sensor includes: a plurality of microlenses formed on a semiconductor substrate with a certain spacing distance; and a protection layer formed over the microlenses, wherein the protection layer includes a first oxide layer which is formed by a plasma enhanced chemical vapor deposition (PECVD) method and a second oxide layer which is formed by a spin on glass (SOG) method over the first oxide layer to maintain sufficient step coverage over chasms between the microlenses.

Abstract: A Cu thin film deposition equipment of a semiconductor device is disclosed for improving deposition speed of a Cu thin film and lowering its corresponding cost. This equipment includes a load lock carrying out the steps before and after wafer processes, an aligner carrying out alignment so that a wafer reaches a desired position, a de-gas chamber removing residue such as gas produced on a surface of a wafer, and a feeding chamber provided with a robot placing the wafer in/out of each chamber. A pre-cleaning chamber cleaning the inside and the outside of a pattern using plasma on a wafer fed by the feeding chamber, a barrier metal deposition chamber, an adhesion glue layer (AGL) flash Cu deposition chamber, a CECVD deposition chamber, and a plasma treatment chamber are also provided with the equipment.

Abstract: A semiconductor has a MIM capacitor formed on the same level with a dual damascene Cu line. The semiconductor includes a first insulating interlayer with first contact holes, first metal lines formed in the first contact holes, and second and third insulating interlayers including the first metal lines. Second and third contact holes are formed in the second insulating interlayer to expose some region of the first metal lines, a trench is formed in the third insulating interlayer corresponding to the second and third contact holes, and a capacitor structure is formed in the second contact hole and the trench above the second contact hole. Second metal lines fill the second and third contact holes and the trenches above the second and third contact holes.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: A semiconductor has a MIM capacitor formed on the same level with a dual damascene Cu line. The semiconductor includes a first insulating interlayer with first contact holes, first metal lines formed in the first contact holes, and second and third insulating interlayers including the first metal lines. Second and third contact holes are formed in the second insulating interlayer to expose some region of the first metal lines, a trench is formed in the third insulating interlayer corresponding to the second and third contact holes, and a capacitor structure is formed in the second contact hole and the trench above the second contact hole. Second metal lines fill the second and third contact holes and the trenches above the second and third contact holes.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: A Cu thin film deposition equipment of a semiconductor device is disclosed for improving deposition speed of a Cu thin film and lowering its corresponding cost. This equipment includes a load lock carrying out the steps before and after wafer processes, an aligner carrying out alignment so that a wafer reaches a desired position, a de-gas chamber removing residue such as gas produced on a surface of a wafer, and a feeding chamber provided with a robot placing the wafer in/out of each chamber. A pre-cleaning chamber cleaning the inside and the outside of a pattern using plasma on a wafer fed by the feeding chamber, a barrier metal deposition chamber, an adhesion glue layer (AGL) flash Cu deposition chamber, a CECVD deposition chamber, and a plasma treatment chamber are also provided with the equipment.

Abstract: Disclosed is a method of forming a copper wiring in a semiconductor device. A copper barrier metal layer and a copper seed layer are sequentially formed along the surface of an interlayer insulating film including damascene patterns. In a state that a wafer is then loaded onto an electrical plating apparatus in which a copper plating solution is filled and a negative (−) power supply is also applied to the wafer, copper is plated so that the damascene patterns are sufficiently filled, thereby forming a copper layer. Next, the copper layer is polished in the plating solution by means of the electro-polishing process by changing the negative (−) power supply to the positive (+) power supply. Due to this, the surface of the copper layer is flat over the entire wafer. Thereafter, a chemical mechanical polishing process is performed until the surface of the interlayer insulating film is exposed, thereby forming copper wirings within the damascene patterns.

Abstract: A Cu thin film deposition equipment of a semiconductor device is disclosed for improving deposition speed of a Cu thin film and lowering its corresponding cost. This equipment includes a load lock carrying out the steps before and after wafer processes, an aligner carrying out alignment so that a wafer reaches a desired position, a de-gas chamber removing residue such as gas produced on a surface of a wafer, and a feeding chamber provided with a robot placing the wafer in/out of each chamber. A pre-cleaning chamber cleaning the inside and the outside of a pattern using plasma on a wafer fed by the feeding chamber, a barrier metal deposition chamber, an adhesion glue layer (AGL) flash Cu deposition chamber, a CECVD deposition chamber, and a plasma treatment chamber are also provided with the equipment.

Abstract: A method of manufacturing a copper metal wiring in a semiconductor device, by which a plasma process is performed before a diffusion barrier layer is formed and a chemical pre-process using a chemical enhancer is performed so that copper is deposited to form a metal wiring by a chemically enhanced chemical vapor deposition (CECVD) method. The method allows the chemical enhancer to be adhered on the diffusion barrier layer uniformly and stably; therefore, improving the deposition property of a copper thin film.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: A Cu thin film deposition equipment of a semiconductor device is disclosed for improving deposition speed of a Cu thin film and lowering its corresponding cost. This equipment includes a load lock carrying out the steps before and after wafer processes, an aligner carrying out alignment so that a wafer reaches a desired position, a de-gas chamber removing residue such as gas produced on a surface of a wafer, and a feeding chamber provided with a robot placing the wafer in/out of each chamber. A pre-cleaning chamber cleaning the inside and the outside of a pattern using plasma on a wafer fed by the feeding chamber, a barrier metal deposition chamber, an adhesion glue layer (AGL) flash Cu deposition chamber, a CECVD deposition chamber, and a plasma treatment chamber are also provided with the equipment.

Abstract: A semiconductor has a MIM capacitor formed on the same level with a dual damascene Cu line. The semiconductor includes a first insulating interlayer with first contact holes, first metal lines formed in the first contact holes, and second and third insulating interlayers including the first metal lines. Second and third contact holes are formed in the second insulating interlayer to expose some region of the first metal lines, a trench is formed in the third insulating interlayer corresponding to the second and third contact holes, and a capacitor structure is formed in the second contact hole and the trench above the second contact hole. Second metal lines fill the second and third contact holes and the trenches above the second and third contact holes.