Abstract: A parallel test board preferably includes a plurality of serial slots connected to a motherboard and a number of parallel slots connected to the motherboard in parallel with each other. The motherboard provides an actual operational environment for devices under test (DUTs). DUTs are mounted in the slots. Using a plurality of serial slots, distorted timings due to one serial slot (e.g., an extension slot) have an influence on the other serial slot (e.g., a reference slot), as well as on the parallel slots. In this manner, a timing margin failure occurring during a multi-bank operation can be effectively detected. The slots to which the DUTs are mounted preferably have a socket structure with a support block having contact pins arranged thereon. Each of the contact pins preferably has a module contact part configured to contact a tab of the DUT and a board contact part configured to contact conductive wiring patterns of an intermediation board.

Abstract: A parallel test board preferably includes a plurality of serial slots connected to a motherboard and a number of parallel slots connected to the motherboard in parallel with each other. The motherboard provides an actual operational environment for devices under test (DUTs). DUTs are mounted in the slots. Using a plurality of serial slots, distorted timings due to one serial slot (e.g., an extension slot) have an influence on the other serial slot (e.g., a reference slot), as well as on the parallel slots. In this manner, a timing margin failure occurring during a multi-bank operation can be effectively detected. The slots to which the DUTs are mounted preferably have a socket structure with a support block having contact pins arranged thereon. Each of the contact pins preferably has a module contact part configured to contact a tab of the DUT and a board contact part configured to contact conductive wiring patterns of an intermediation board.

Abstract: A die testing apparatus according to the present invention includes a lead frame having a plurality of die pads, wherein a plurality of bare chips are mounted on the die pads. The bonding pads of each bare chips are connected to a plurality of leads associated with each die pad through a plurality of bonding wires. The die pads are supported by a plurality of tie bars and the leads are supported by an adhesion tape attached to the lead frame. The lead frame is placed in a test socket which includes an under socket having a plurality of slot grooves and an upper socket hinged with the under socket and having a plurality of slot holes and a plurality of test probes contacting the leads of the lead frame.