Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

Abstract: A display device includes: a display panel; a driving voltage generator; a power voltage generator; an input voltage generator; and a timing controller. The display panel is provided with a pixel configured to emit light by using a driving voltage. The driving voltage generator is configured to supply the driving voltage to the pixel. The power voltage generator is configured to generate power voltages for driving of the display panel by using an input voltage, and generating an input voltage sensing value by sensing the input voltage. The input voltage generator is configured to supply the input voltage to the power voltage generator. The timing controller is configured to control an operation of at least one of the driving voltage generator, the power voltage generator, and the input voltage generator according to the input voltage sensing value.

Abstract: The present inventive concept provides a display device including a pixel unit which includes pixels, a sensing unit connected to the pixels through sensing lines, a first power voltage generator connected to the pixels through a first power line and generating a first power voltage for driving the pixels, a second power voltage generator connected to the pixels through the first power line and generating a second power voltage for sensing the pixels, and a timing controller selectively controlling operations of the first power voltage generator and the second power voltage generator according to a driving method of the pixel unit, and a method driving the same.

Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driver which supplies scan signals and sensing control signals to scan lines and sensing control lines, based on a clock signal, a power manager which applies initialization power to initialization lines, a sensor which senses threshold voltages of driving transistors, a detector which detects an error of the initialization lines and outputs line information indicating an initialization line having the error, a timing controller which changes a sensed threshold voltage using the initialization line having the error and generates image data with reference to a changed threshold voltage, and a data driver which supplies a data signal corresponding to the image data to data lines.

Abstract: A display device includes a scale factor provider, a grayscale converter, and pixels. The scale factor provider calculates an n-th scale factor based on n-th input grayscales received during an n-th frame period. The grayscale converter calculates (n+p)th output grayscales by applying the n-th scale factor to (n+p)th input grayscales received during an (n+p)th frame period in a first mode. The pixels output light to display an image based on the (n+p)th output grayscales, where n is an integer greater than 0 and p is an integer greater than 1.

Abstract: A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

Abstract: A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

Abstract: A display device includes a scale factor provider, a grayscale converter, and pixels. The scale factor provider calculates an n-th scale factor based on n-th input grayscales received during an n-th frame period. The grayscale converter calculates (n+p)th output grayscales by applying the n-th scale factor to (n+p)th input grayscales received during an (n+p)th frame period in a first mode. The pixels output light to display an image based on the (n+p)th output grayscales, where n is an integer greater than 0 and p is an integer greater than 1.

Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

Abstract: A display device includes a first power source, a timing controller, and pixels. The timing controller is connected to the first power source through a main line, an auxiliary line, and a detection line. The pixels are commonly connected to the first power source through a first power line. The first power source includes: a main power source connected to the first power line and the main line; an auxiliary power source connected to the auxiliary line; a rectifier connected between the auxiliary power source and the first power line; and a comparator comparing a voltage of the first power line and providing its output to the detection line.

Abstract: A display device includes a first power source, a timing controller, and pixels. The timing controller is connected to the first power source through a main line, an auxiliary line, and a detection line. The pixels are commonly connected to the first power source through a first power line. The first power source includes: a main power source connected to the first power line and the main line; an auxiliary power source connected to the auxiliary line; a rectifier connected between the auxiliary power source and the first power line; and a comparator comparing a voltage of the first power line and providing its output to the detection line.

Abstract: A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driver which supplies scan signals and sensing control signals to scan lines and sensing control lines, based on a clock signal, a power manager which applies initialization power to initialization lines, a sensor which senses threshold voltages of driving transistors, a detector which detects an error of the initialization lines and outputs line information indicating an initialization line having the error, a timing controller which changes a sensed threshold voltage using the initialization line having the error and generates image data with reference to a changed threshold voltage, and a data driver which supplies a data signal corresponding to the image data to data lines.

Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

Abstract: A display device includes a display panel, a power supply, a signal controller configured to generate first and second clock signals having a period, a clock signal generator configured to generate a gate clock signal that is raised to a high level voltage in synchronization with the first clock signal, and that falls to a low level voltage in synchronization with the second clock signal, generate a panel separation signal by comparing a voltage of the gate clock signal with a first reference voltage during a falling period during which the gate clock signal falls, and transfer the panel separation signal to the power supply or the signal controller, and a gate driver configured to sequentially apply a gate signal by using the gate clock signal, wherein the power supply or the signal controller is configured to stop outputting depending on the panel separation signal.

Abstract: The current disclosure relates to a display device including a display panel including a plurality of pixels, and a plurality of gate lines and a plurality of data lines connected to the plurality of pixels, a gate driver applying a gate signal to the plurality of gate lines, a data driver applying a data signal to the plurality of data lines, and a voltage provider configured to generate a gate-on voltage that is gradually changed in one frame and a kickback voltage that is gradually changed in one frame to transmit the gate-on voltage and the kickback voltage to the gate driver.

Abstract: A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

Abstract: A display device includes a display panel, a power supply, a signal controller configured to generate first and second clock signals having a period, a clock signal generator configured to generate a gate clock signal that is raised to a high level voltage in synchronization with the first clock signal, and that falls to a low level voltage in synchronization with the second clock signal, generate a panel separation signal by comparing a voltage of the gate clock signal with a first reference voltage during a falling period during which the gate clock signal falls, and transfer the panel separation signal to the power supply or the signal controller, and a gate driver configured to sequentially apply a gate signal by using the gate clock signal, wherein the power supply or the signal controller is configured to stop outputting depending on the panel separation signal.