Patents by Inventor Si Hao Vincent Yeo

Si Hao Vincent Yeo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230178428
    Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Thorsten Meyer, Fee Hoon Wendy Wong, Thomas Behrens, Eric Lopez Bonifacio, Chau Fatt Chiang, Irmgard Escher-Poeppel, Giovanni Ragasa Garbin, Martin Gruber, Tien Shyang Law, Mohamad Azian Mohamed Azizi, Si Hao Vincent Yeo
  • Publication number: 20230170329
    Abstract: A method of forming a semiconductor package includes providing a metal baseplate including a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.
    Type: Application
    Filed: August 16, 2022
    Publication date: June 1, 2023
    Inventors: Sock Chien Tey, Keck Tim Ang, Chan Lam Cha, Chau Fatt Chiang, Badrul Hisyam Ismail, Desmond Jenn Yong Loo, Ronizan Mohd Salleh, Norliza Morban, Si Hao Vincent Yeo, Chee Mun Wai, Fee Hoon Wendy Wong
  • Publication number: 20220199478
    Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Inventors: Si Hao Vincent Yeo, Chan Lam Cha, Ying Dieh Cheong, Chau Fatt Chiang, Cher Hau Danny Koh, Wern Ken Daryl Wee, Swee Kah Lee, Desmond Jenn Yong Loo, Fortunato Lopez, Norliza Morban, Khay Chwan Andrew Saw, Sock Chien Tey, Mei Yong Wang
  • Patent number: 11296000
    Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Patent number: 10937744
    Abstract: A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Wern Ken Daryl Wee, Sock Chien Tey, Si Hao Vincent Yeo
  • Publication number: 20200350222
    Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 5, 2020
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Publication number: 20200273813
    Abstract: A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Applicant: Infineon Technologies AG
    Inventors: Wern Ken Daryl Wee, Sock Chien Tey, Si Hao Vincent Yeo
  • Patent number: 10741466
    Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Publication number: 20190157173
    Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo