Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract: A method of operating a non-volatile memory can include backing-up first data successfully programmed to a first target page of a non-volatile memory to provide local back-up data. A determination can be made that programming of second data to the first target page has failed and the local back-up data can be programmed to a second target page in a second block of the non-volatile memory.

Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

Abstract: A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded.

Abstract: A method of operating a non-volatile memory can include backing-up first data successfully programmed to a first target page of a non-volatile memory to provide local back-up data. A determination can be made that programming of second data to the first target page has failed and the local back-up data can be programmed to a second target page in a second block of the non-volatile memory.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a TCM modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract: A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded.

Abstract: A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded.

Abstract: A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded.

Abstract: A disc interface, a disc interface system having the same, and a disc interfacing method may be provided. The disc interface may receive a reduced quantity of test command information at a lower speed which may correspond to an operation speed of a general test apparatus to automatically generate a real-time testbench signal. The digital unit of the disc interface may be operated at an actual operation speed though the test command information and debugging data may be input and output at a lower speed. Thus, digital circuits operating at a high speed may be tested using an less expensive test apparatus.