Abstract: A circuit and method for power gating is provided. The circuit includes a switch circuit and a modulation oscillator. The switch circuit is connected between a circuit module and a power network having a target level. The switch circuit receives a control signal at its control signal input terminal to gate a connection between the circuit module and the power network under the control of the control signal. The switch circuit is connected to the circuit module at a first node. A modulation oscillator enabling signal input terminal is connected to a gating signal for enabling the modulation oscillator, a modulation oscillator control signal input terminal is connected to the first node, and an modulation oscillator output terminal is connected to the control signal input terminal of the switch circuit. The oscillation signal outputted from the modulation oscillator is modulated by the level of the first node.

Abstract: A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit.

Abstract: A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit.

Abstract: A circuit and method for power gating is provided. The circuit includes a switch circuit and a modulation oscillator. The switch circuit is connected between a circuit module and a power network having a target level. The switch circuit receives a control signal at its control signal input terminal to gate a connection between the circuit module and the power network under the control of the control signal. The switch circuit is connected to the circuit module at a first node. A modulation oscillator enabling signal input terminal is connected to a gating signal for enabling the modulation oscillator, a modulation oscillator control signal input terminal is connected to the first node, and an modulation oscillator output terminal is connected to the control signal input terminal of the switch circuit. The oscillation signal outputted from the modulation oscillator is modulated by the level of the first node.