Abstract: A power amplifying circuit includes a switching circuit, an amplifier and a load. The switching circuit receives a first supply voltage and a second supply voltage. When the switching circuit is in a first operation mode, the first supply voltage is provided to a node. When the switching circuit is in a second operation mode, the second supply voltage is provided to the node. The amplifier receives a first input signal and a second input signal, and outputs a first output signal and a second output signal from a first output terminal and a second output signal, respectively. The load includes a first inductor and a second inductor. The first inductor is connected between the node and the first output terminal. The second inductor is connected between the node and the second output terminal.

Abstract: A method for asymmetrically scheduling buffer cache of disk array. The method including: (1) detecting whether access from a upper layer is hit in a buffer cache, proceeding to (7) if yes, and proceeding to (2) if no; (2) detecting whether the buffer cache is full, proceeding to (3) if yes, and proceeding to (5) if no; (3) detecting whether the number of pages of a sacrificial disk is greater than a threshold, proceeding to (4) if yes, and proceeding to (6) if no; (4) selecting and replacing a cold page of the sacrificial disk; (5) buffering data requested by a user in a blank page in the buffer cache; (6) selecting and replacing all cold pages of the buffer cache; and (7) reading or writing the data, and changing positions or status thereof in pages of the buffer cache.

Abstract: Systems and techniques are described for optimizing communications between a client and a server. Specifically, in some embodiments, an executing script on a client can send a resource request to a server. In response, the server can send an optimized version of the resource back to the client. The client can then reconstruct the resource from the optimized version of the resource.

Abstract: A method for asymmetrically scheduling buffer cache of disk array. The method including: (1) detecting whether access from a upper layer is hit in a buffer cache, proceeding to (7) if yes, and proceeding to (2) if no; (2) detecting whether the buffer cache is full, proceeding to (3) if yes, and proceeding to (5) if no; (3) detecting whether the number of pages of a sacrificial disk is greater than a threshold, proceeding to (4) if yes, and proceeding to (6) if no; (4) selecting and replacing a cold page of the sacrificial disk; (5) buffering data requested by a user in a blank page in the buffer cache; (6) selecting and replacing all cold pages of the buffer cache; and (7) reading or writing the data, and changing positions or status thereof in pages of the buffer cache.

Abstract: Virtual storage arrays consolidate branch data storage at data centers connected via wide area networks. Virtual storage arrays appear to storage clients as local data storage; however, virtual storage arrays actually store data at the data center. Virtual storage arrays overcome bandwidth and latency limitations of the wide area network by predicting and prefetching storage blocks, which are then cached at the branch location. Virtual storage arrays leverage an understanding of the semantics and structure of high-level data structures associated with storage blocks to predict which storage blocks are likely to be requested by a storage client. Virtual storage arrays may use proximity-based, heuristic-based, and access time-based prefetching to predict high-level data structure entities that are likely to be accessed by the storage client. Virtual storage arrays then identify and prefetch storage blocks corresponding with the predicted high-level data structure entities.

Abstract: A single-ended optimized storage protocol enables storage clients or other devices to direct a remote data storage to copy data. In response to commands via the protocol, a remote data storage can copy portions of a data stream at the remote data storage to destination storage locations within the same or a different data stream. The protocol may be utilized for optimized transfer of data via a network to a remote data storage. An initial data stream is divided into segments. Redundant segments are removed from the data stream to form an optimized data stream, which is transferred to the remote data storage. Commands are issued to the remote data storage using the protocol to direct the remote data storage to reconstruct the initial data stream at the remote data storage using the optimized data stream and optionally segments from other data streams previously transferred to the remote data storage.

Abstract: The present invention discloses a multi-channel timing recovery device capable of generating a common clock for processing a plurality of data channel signals, comprising: a first channel timing recovery circuit, and a second channel timing recovery circuit. The said first channel timing recovery circuit includes a first detecting circuit capable of detecting phase and/or frequency, an oscillation control circuit, an oscillator and a feedback circuit, and is operable to generate the common clock according to a first channel signal which could be a clock signal or a data signal. The said second channel timing recovery circuit includes a second phase detecting circuit, a second phase control circuit and a second clock output circuit, and is operable to generate a second clock according to the common clock and determine the phase of the second clock according to a second channel signal which is a data signal.

Abstract: The present invention discloses a multi-channel timing recovery device capable of generating a common clock for processing a plurality of data channel signals, comprising: a first channel timing recovery circuit, and a second channel timing recovery circuit. The said first channel timing recovery circuit includes a first detecting circuit capable of detecting phase and/or frequency, an oscillation control circuit, an oscillator and a feedback circuit, and is operable to generate the common clock according to a first channel signal which could be a clock signal or a data signal. The said second channel timing recovery circuit includes a second phase detecting circuit, a second phase control circuit and a second clock output circuit, and is operable to generate a second clock according to the common clock and determine the phase of the second clock according to a second channel signal which is a data signal.

Abstract: A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.

Abstract: An equalizer includes a first sampler, a second sampler, and an equalization circuit. The first sampler is used for sampling an input data to generate an output data, and the second sampler is used for sampling the input data to generate an edge information. The equalization circuit is coupled to the first sampler and the second sampler, and includes an equalization unit and a control unit. The equalization unit performs an equalization operation on an original input data in order to generate the input data according to a plurality of tap coefficients. The control unit is coupled to the equalization unit, for adjusting the plurality of tap coefficients according to the output data and the edge information.

Abstract: A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.

Abstract: A system of network proxies distributes data to multiple servers. Each network proxy is associated with a server. A network proxy intercepts a client request for data. If the network proxy determines that the request can be served using a copy of data stored on the local server, rather than the data stored on a remote server, it diverts the request to the local server. If the network proxy determines that the request cannot be served using a data from the local server, the network proxy diverts the request to a remote server storing the primary copy of the data. A server map specifies the locations of the primary copies of data. When a primary copy of data is updated on one of the servers, the associated network proxy propagates the updated data to the other servers. The servers can provide data from files, e-mail services, databases, or multimedia services.

Abstract: A method and device of the power saving for transmitting a signal is provided. The method comprises the steps of: transmitting a test signal with a first test amplitude from a local terminal, wherein the first test amplitude is selected from a plurality of preset amplitudes; acknowledging that the test signal with the first test amplitude has been received by a remote terminal if an acknowledgement signal is transmitted from the remote terminal for a response to the test signal; and transmitting a data signal having a data amplitude based on the first test amplitude. The device can transmit the data signal with a small data signal amplitude by the method to achieve the saving power.

Abstract: Serial clustering uses two or more network devices connected in series via a local and/or wide-area network to provide additional capacity when network traffic exceeds the processing capabilities of a single network device. When a first network device reaches its capacity limit, any excess network traffic beyond that limit is passed through the first network device unchanged. A network device connected in series with the first network device intercepts and will process the excess network traffic provided that it has sufficient processing capacity. Additional network devices can process remaining network traffic in a similar manner until all of the excess network traffic has been processed or until there are no more additional network devices. Network devices may use rules to determine how to handle network traffic. Rules may be based on the attributes of received network packets, attributes of the network device, or attributes of the network.

Abstract: Network proxies reduce server latency in response to series of requests from client applications. Network proxies intercept messages clients and a server. Intercepted client requests are compared with rules. When client requests match a rule, additional request messages are forwarded to the server on behalf of a client application. In response to the additional request messages, the server provides corresponding response messages. A network proxy intercepts and caches the response messages. Subsequent client requests are intercepted by the network application proxy and compared with the cached messages. If a cached response message corresponds with a client request message, the response message is returned to the client application immediately instead of re-requesting the same information from the server. A server-side network proxy can compare client requests with the rules and send additional request messages. The corresponding response messages can be forwarded to a client-side network proxy for caching.

Abstract: Network devices include hosted virtual machines and virtual machine applications. Hosted virtual machines and their applications implement additional functions and services in network devices. Network devices include data taps for directing network traffic to hosted virtual machines and allowing hosted virtual machines to inject network traffic. Network devices include unidirectional data flow specifications, referred to as hyperswitches. Each hyperswitch is associated with a hosted virtual machine and receives network traffic received by the network device from a single direction. Each hyperswitch processes network traffic according to rules and rule criteria. A hosted virtual machine can be associated with multiple hyperswitches, thereby independently specifying the data flow of network traffic to and from the hosted virtual machine from multiple networks.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: Network devices include hosted virtual machines and virtual machine applications. Hosted virtual machines and their applications implement additional functions and services in network devices. Network devices include data taps for directing network traffic to hosted virtual machines and allowing hosted virtual machines to inject network traffic. Network devices include unidirectional data flow specifications, referred to as hyperswitches. Each hyperswitch is associated with a hosted virtual machine and receives network traffic received by the network device from a single direction. Each hyperswitch processes network traffic according to rules and rule criteria. A hosted virtual machine can be associated with multiple hyperswitches, thereby independently specifying the data flow of network traffic to and from the hosted virtual machine from multiple networks.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: A clock and data recovery device, a sampler and a sampling method thereof are provided. The sampler includes a phase generation circuit and a first edge sampling circuit electrically connected with the phase generation circuit. The phase generation circuit is configured to generate a plurality of first phases which have different phase values. The first edge sampling circuit is configured to sample a plurality of first edge values of a plurality of bits of a data signal according to the first phases so that the clock and data recovery device determines a clock of the data signal according to the first edge values.