Patents by Inventor Si Yoon Lee

Si Yoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153813
    Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Si-Woo Lee, Byung Yoon Kim
  • Publication number: 20240147693
    Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Byung Yoon Kim, Sheng Wei Yang, Si-Woo Lee, Mark Zaleski
  • Patent number: 9599446
    Abstract: A small sealing gauge may include a body that is attached to a site to be measured, a lever that linearly moves by contact with a moving part while moving in a state of being inserted into a hole of the body, and a dial gauge that is inserted to a back side of the hole in the body to measure an amount of movement of the lever through contact with the lever.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: March 21, 2017
    Assignee: Hyundai Motor Company
    Inventors: Tae Il Min, Si Yoon Lee
  • Publication number: 20160033253
    Abstract: A small sealing gauge may include a body that is attached to a site to be measured, a lever that linearly moves by contact with a moving part while moving in a state of being inserted into a hole of the body, and a dial gauge that is inserted to a back side of the hole in the body to measure an amount of movement of the lever through contact with the lever.
    Type: Application
    Filed: December 15, 2014
    Publication date: February 4, 2016
    Applicant: Hyundai Motor Company
    Inventors: Tae Il MIN, Si Yoon Lee