Patents by Inventor Siak Chon Kee

Siak Chon Kee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9287872
    Abstract: In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: March 15, 2016
    Assignee: LATTICESEMICONDUCTORCORPORATION
    Inventors: Siak Chon Kee, Giap Tran, Brad Sharpe-Geisler
  • Publication number: 20150372679
    Abstract: In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Siak Chon Kee, Giap Tran, Brad Sharpe-Geisler
  • Patent number: 7187530
    Abstract: An electrostatic discharge protective circuit may comprise a low-pass filter and a high-pass filter to receive and filter signals of a supply line. Control logic may receive output signals of the low-pass and high-pass filters and may operate a gateable channel to shunt current of the supply line dependent on the output signals from the filters.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: March 6, 2007
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Craig Thomas Salling, Siak Chon Kee, Pierre Dermy
  • Publication number: 20040125521
    Abstract: An electrostatic discharge protective circuit may comprise a low-pass filter and a high-pass filter to receive and filter signals of a supply line. Control logic may receive output signals of the low-pass and high-pass filters and may operate a gateable channel to shunt current of the supply line dependent on the output signals from the filters.
    Type: Application
    Filed: February 4, 2003
    Publication date: July 1, 2004
    Inventors: Craig Thomas Salling, Siak Chon Kee, Pierre Dermy