Patents by Inventor Siamack Haghighi

Siamack Haghighi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6434639
    Abstract: A method and apparatus are for use with a computer system. Write requests to store data in one or more memory locations that are collectively associated with a cache line are received. The first requests are combined to furnish a memory operation. The computer system may include a peripheral device that furnishes a stream of data to be stored in a memory, and the apparatus may include first and second interfaces, a queue and logic. The first interface is adapted to convert a portion of the stream of data into a first request, and the queue is adapted to store the second request. The logic is adapted to determine if the first and second requests target memory locations that are collectively associated with a cache line and based on the determination, selectively combine the first and second requests. The second interface is adapted to furnish a memory operation in response to the combination of the first and second requests. The requests may be, as examples, read requests and/or write requests.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: August 13, 2002
    Assignee: Intel Corporation
    Inventor: Siamack Haghighi
  • Patent number: 6178265
    Abstract: A method and apparatus for motion vector compression is described. Compression is performed in the context of a two-dimensional processing system in which two-dimensional frames are each encoded into minimum-error motion vectors. For each frame, the minimum-error motion vectors are compressed by histogramming at least one minimum-error motion vector to generate at least one histogram peak. N most dominant peaks represent the frequency of occurrence of N most dominant motion vectors. Compression further requires that each minimum-error motion vector is mapped to one of the N most dominant motion vectors. Before undergoing histogramming, each minimum-error motion vector may be mapped to a null motion vector (0, 0) if the minimum-error motion vector does not provide a significant improvement over the frame-to-frame correlation error associated with the null motion vector for the frame.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: January 23, 2001
    Assignee: Intel Corporation
    Inventor: Siamack Haghighi
  • Patent number: 6044440
    Abstract: A system and method of transferring data in multi-cache systems. The method includes transmitting a first segment of a data stream from a first cache to a second cache. The method also includes retransmitting the first segment of the data stream from the second cache to a main memory. The method further includes generating a second segment of the data stream and completing a transfer of the second segment to the first cache before completing the retransmission of the first segment from the second cache to the main memory.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventor: Siamack Haghighi
  • Patent number: 5539664
    Abstract: A subset of signals corresponding to a two-dimensional set of signals is stored into an area of computer memory smaller than the two-dimensional set for processing. Additional signals are sequentially stored in the computer memory area and processed until the entire set of signals has been processed. In a preferred embodiment, motion estimation processing is performed by sequentially transmitting video signals corresponding to portions of a search region of a previous frame from off-chip memory and storing the video signals to on-chip memory for comparison with a reference block of a current frame. The invention provides reduced computer memory usage, reduced signal transfer, and more uniform signal transfer in computer-implemented processing, such as motion estimation processing, that involves two-dimensional caching.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: July 23, 1996
    Assignee: Intel Corporation
    Inventors: Siamack Haghighi, Brian Astle