Patents by Inventor Siamak Jonaidi

Siamak Jonaidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6354859
    Abstract: A cover assembly for IC chip has a lid portion and a retractable chip depressor member extendable from the underside of the lid portion along the lid's z-axis. When the cover assembly is mounted over the chip cavity of an IC socket and is properly indexed in the x-y plane of the socket, the retractable chip depressor member is retractable advanced along the z-axis of the lid portion to contact and depress the chip in the socket's chip cavity by a force that is parallel to the z-axis of the chip cavity and that is normal to the IC chip.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: March 12, 2002
    Assignee: Cerprobe Corporation
    Inventors: Nasser Barabi, Siamak Jonaidi
  • Patent number: 6220870
    Abstract: An I/C chip socket is provided with a separate docking platform having a seating surface with an array of locator openings for receiving and fixing the position of the I/O contacts of an I/C chip such as the solder balls of a BGA. The docking platform is depressibly mounted in the base portion of the socket over the tips of an array of pogo pins. The docking platform acts to precisely center the I/O contacts of the I/C chip seated thereon with the pogo pin tips.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: April 24, 2001
    Assignee: Cerprobe Corporation
    Inventors: Nasser Barabi, Siamak Jonaidi
  • Patent number: 6208155
    Abstract: An improved probe tip for making electrical contact with a solder ball of an integrated circuit device such as a BGA includes two perimeter point structures having interior angled edges which form a front hollow region in the probe tip for receiving the solder ball of a BGA. Each of the interior edges of the point structures includes an angled medial contact zone which tangentially contacts the solder ball received in the hollow region of the tip to produce minimal distortion of the solder ball. The method of the invention permits electrical contact with a solder ball of a BGA with minimal deformation of the solder ball. In accordance with the method, the contact between the probe tip and the solder ball is limited to tangential contacts around the solder ball below the solder ball's apex.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: March 27, 2001
    Assignee: Cerprobe Corporation
    Inventors: Nasser Barabi, Siamak Jonaidi
  • Patent number: 6091155
    Abstract: A ball grid array (BGA) land pattern. In the present invention, a capture pad is disposed on a substrate. The capture pad is electrically coupled to a via which is formed into the substrate. A substantially rectangularly-shaped landing pad is also disposed on the substrate proximate to the capture pad. The substantially rectangularly-shaped landing pad is electrically coupled to the capture pad. In one embodiment, an electrically conductive connecting region electrically connects the substantially rectangularly-shaped landing pad to the capture pad. More specifically, the electrically conductive connecting region has a first end coupled to the capture pad and a second end coupled to the substantially rectangularly-shaped landing pad.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: July 18, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Siamak Jonaidi
  • Patent number: 6042387
    Abstract: A connector system (20) connects a leadless integrated circuit (IC) device (22) to a printed circuit (PC) board (24) by means of a contact array (26). The contact array (26) connects input-output (I/O) contacts on the IC device (22) to corresponding circuit contacts (28) on PC board (24). The contact array (26) is a generally thin, flexible and rectangular shaped element that is sandwiched between the PC board (24) and the IC device (22). The contact array (26) has a plurality of square cells (30) that are each a portion of the array (26) and are formed from a planar body (32) of a suitable conductive material, such as beryllium copper, sandwiched between suitable insulating films, formed from polyimide. Each cell is divided into a first pair (34) of contact elements (36) extending above the plane of the body (32) and a second pair (38) of contact elements (36) extending below the plane of the body (32).
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: March 28, 2000
    Assignee: Oz Technologies, Inc.
    Inventor: Siamak Jonaidi
  • Patent number: 5834705
    Abstract: An apparatus for modifying a printed circuit board comprised of a nonconductively adhering flexible circuitized substrate, the flexible circuitized substrate having a conductive circuit trace composed of one or more layers of thin wires sandwiched between two or more layers of flexible insulating protective material. The wires forming the circuit trace of the flexible substrate and the conductors forming the circuitry in and on the printed circuit board are electrically interconnected at appropriate predetermined positions by establishing conductive paths through portions of the insulating layers of the flexible circuitized substrate. Circuit components can also be affixed to either the flexible circuitized substrate or to the printed circuit board or to both after the flexible circuitized substrate has been affixed to the printed circuit board.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: November 10, 1998
    Assignee: Silicon Graphics, Inc.
    Inventor: Siamak Jonaidi
  • Patent number: 5400948
    Abstract: A method for fabricating a printed circuit board for high pin count surface mount pin grid arrays is provided where surface mount pads for soldering a surface mount pin grid array package are isolated by solder mask layers. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.
    Type: Grant
    Filed: February 2, 1994
    Date of Patent: March 28, 1995
    Assignee: Aptix Corporation
    Inventors: Vijay M. Sajja, Siamak Jonaidi
  • Patent number: 5313021
    Abstract: A printed circuit board is provided with surface mount pads for soldering a surface mount pin grid array package. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: May 17, 1994
    Assignee: Aptix Corporation
    Inventors: Vijay M. Sajja, Siamak Jonaidi