Patents by Inventor Sian Lu
Sian Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963348Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.Type: GrantFiled: August 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
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Patent number: 11723194Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.Type: GrantFiled: March 5, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
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Publication number: 20220384462Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Geng-Cing LIN, Ze-Sian LU, Meng-Sheng CHANG, Chia-En HUANG, Jung-Ping YANG, Yen-Huei CHEN
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Publication number: 20220384644Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.Type: ApplicationFiled: July 25, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ze-Sian Lu, Ting-Wei Chiang, Pin-Dai Sue, Jung-Hsuan Chen, Hui-Wen Li
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Patent number: 11469321Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.Type: GrantFiled: February 27, 2020Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ze-Sian Lu, Ting-Wei Chiang, Pin-Dai Sue, Jung-Hsuan Chen, Hui-Wen Li
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Publication number: 20220285375Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Inventors: Geng-Cing LIN, Ze-Sian LU, Meng-Sheng CHANG, Chia-En HUANG, Jung-Ping YANG, Yen-Huei CHEN
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Publication number: 20210273093Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.Type: ApplicationFiled: February 27, 2020Publication date: September 2, 2021Inventors: Ze-Sian Lu, Ting-Wei Chiang, Pin-Dai Sue, Jung-Hsuan Chen, Hui-Wen Li
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Publication number: 20160091566Abstract: A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.Type: ApplicationFiled: December 23, 2014Publication date: March 31, 2016Inventors: Sian Lu, Hao Wang
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Patent number: 9291674Abstract: A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.Type: GrantFiled: December 23, 2014Date of Patent: March 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Sian Lu, Hao Wang
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Patent number: 8880965Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.Type: GrantFiled: November 21, 2012Date of Patent: November 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Wanggen Zhang, Sian Lu, Shayan Zhang
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Patent number: 8736302Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.Type: GrantFiled: September 11, 2012Date of Patent: May 27, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xu Zhang, Chad J. Lerma, Kai Liu, Sian Lu, Hao Wang, Shayan Zhang, Wanggen Zhang
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Publication number: 20140040688Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.Type: ApplicationFiled: November 21, 2012Publication date: February 6, 2014Inventors: Wanggen Zhang, Sian Lu, Shayan Zhang
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Publication number: 20130300497Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.Type: ApplicationFiled: September 11, 2012Publication date: November 14, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Xu Zhang, Chad J. Lerma, Kai Liu, Sian Lu, Hao Wang, Shayan Zhang, Wanggen Zhang
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Publication number: 20100283179Abstract: A TiON, TaON or ZrON thin film is fabricated through an easy process. The film is corrosion resistant, electric conductive and decorative. The process uses no chloride (Cl) and so is environmental protected. The present disclosure is fit for mass production.Type: ApplicationFiled: January 20, 2010Publication date: November 11, 2010Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCHInventors: Zih-Sian Lu, Keng-Shen Liu, Wen-Biing Ou Yang, Chih-Hung Wu