Patents by Inventor Sian Yong Khoo

Sian Yong Khoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7320933
    Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: January 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
  • Patent number: 7112048
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Publication number: 20040198033
    Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 7, 2004
    Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
  • Patent number: 6720666
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: April 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Publication number: 20040036170
    Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 26, 2004
    Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
  • Patent number: 6692987
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Publication number: 20030211660
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 13, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Publication number: 20030211659
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 13, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Publication number: 20030148557
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 7, 2003
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Patent number: 5956233
    Abstract: A high density single inline memory module (140) comprising a printed circuit board (132) and at least one integrated circuit module (130) attached to the first side (134) of the printed circuit board (132), wherein the integrated circuit modules (130) each including first and second integrated circuit packages (30) stackably and electrically connected together is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 21, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Chee Kiang Yew, Kian Teng Eng, Sian Yong Khoo, Bok Leng Ser