Abstract: An antifuse contact (30) cleaning method and the resulting antifuse (10) uses limited-reaction Ti/.alpha.-Si contact cleaning. The method includes the steps of placing a limited-reaction metal such as Ti (22, 24, 34) at the interface of a metal (20)/.alpha.-Si (32)/metal (36) antifuse contact (30). The method is to react the thin reaction metal (22, 24, 34) at a temperature of less than approximately 450.degree. C. to remove the native interface layer of the metal (20)/.alpha.-Si (32)/metal (36) antifuse to, thereby, clean the metal (20)/.alpha.-Si (32)/metal (36) antifuse contact (30).

Abstract: A method of making a semiconductor device with self-aligned ohmic contacts which exhibits substantially reduced shadowing. The gate material is covered with a layer of gate mask material. The gate mask material is selectively removed to form a gate mask having sidewalls with slope profiles of an inclination sufficient to avoid maximum shadow encroachment for subsequent material depositions. Gate mask material is characterized by the sidewalls having an angularity relative to the surface of the substrate which is at least as great as the angle of evaporative deposition of ohmic contact material from a point evaporative source to the extreme gate position on the substrate.

Abstract: A self-aligned MESFET is formed by implanting a first (channel) region in a first surface portion of a gallium arsenide substrate. A dielectric layer is formed on the surface of the substrate and portions of this layer are selectively removed, to leave a relatively thick substitutional gate mesa overlying a first surface portion of the first region and a relatively thin protective portion, contiguous with the substitutional gate, overlying a second surface portion of the first region, so that the substitutional gate has sidewalls extending above the protective portion. Sidewall spacers are formed contiguous with the sidewalls of the substitutional gate, so as to overlie surface portions of the protective portion of the dielectric layer contiguous with the substitutional gate. Ions are implanted into the substrate using the substitutional gate and the sidewall spacers as a mask, thereby forming source and drain regions in the first region.

Abstract: A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device.

Abstract: A post-ion implantation annealing technique is provided to remove implantation damage in the active region of III-V (e.g., GaAs) semiconductor devices formed in a III-V semi-insulating substrate and separated by a field region. The technique involves applying a dielectric encapsulation selectively over the device active area and annealing in a controlled reducing atmosphere which includes the Group V element (e.g., arsenic). The dielectric encapsulant over the active region permits migration of the species employed to render the substrate semi-insulating (e.g., Cr in GaAs substrates), thereby resulting in high carrier mobility in the active region. Without encapsulation, migration of the species in the field region is substantially suppressed, thereby resulting in good inter-device isolation.