Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Abstract: An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.

Abstract: Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist.

Abstract: Integrated circuit packages with a signal routing control through a given direction are disclosed. A disclosed integrated circuit package includes a plurality of interconnects. A first logic circuitry of a first integrated circuit may produce a first signal that may be transmitted to a second integrated circuit. The integrated circuit package further includes interconnect circuitry disposed between the first and second integrated circuits. Multiplexing circuitry may select the first signal from second logic circuitry when the first logic circuitry is defective and may direct the signal as output signal to the second integrated circuit through a given interconnect.

Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Abstract: A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal routing that is mask-programmable to supply any of a plurality of clock signals to any of the IO circuits in the subplurality. Core circuitry of the structured ASIC includes clock signal distribution circuitry, and that distribution circuitry can supply (via buffers associated with each subplurality) the same plurality of clock signals to the routing circuitry associated with all of the subpluralities.