Abstract: A single integrated-circuit color camera chip is color sensitive by grouping closely-adjoining light-detecting cells in a photodiode array into triplets. Each pixel of the sensor includes both a read transistor and a write transistor. Each cells in the triplet is similar, but each cell is associated with a color filter of a different color, with red, green or blue cells in an R-G-B system. The proximity and small size of the cells in a triplet allows accurate color differentiation each pixel. Color information is adjusted on-chip for color, brightness and contrast before being sent to an external read device or display device. The color filter is a series of passive layers formed on the integrated circuit surface permitting the selective transmission of light or electromagnetic radiation of certain frequency ranges. The filter may be coated onto a semiconductor wafer after the latter has undergone conventional MOS process steps.

Abstract: An integrated circuit functions as an image detector providing an output signal representing the detected image. A two dimensional array of sensor cells is formed in rows and columns. A digital timing control means has outputs for providing timing signals. An address encoder is coupled to receive timing control signals from the digital timing control means. Each sensor cell has a photodiode and a first transistor having a first gate and having a source/drain circuit for precharging the cell and a second transistor having a second gate and a source/drain circuit for reading from the photodiode. The sensor cells are adapted for sensing electromagnetic radiation incident thereon. A plurality of sensor data amplifiers receives data from the cells. Means is provided for reading data from the cells into the sensor data amplifiers, and the sense amplifiers include an output circuit.

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.