Patents by Inventor Siang Yeong Tan

Siang Yeong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11343906
    Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Tai Loong Wong, Fern Nee Tan, Tin Poay Chuah, Min Suet Lim, Siang Yeong Tan
  • Publication number: 20220091644
    Abstract: A first circuit to receive from a sensor a thermal condition of a voltage regulator while circuitry comprising the voltage regulator is to regulate delivery of power to a power domain having first and second components. The circuitry is to control a first power consumption rate of the first component based on a first parameter and control a second power consumption rate of the second component based on a second parameter. The first circuit monitors the thermal condition and generates an evaluation result based on a test criterion. A second circuit receives from the first circuit a signal based on the evaluation result. Based on the signal, the second circuit is to signal the circuitry to change the first parameter. An amount of any change to the second parameter based on the evaluation result is different than an amount of change to the first parameter based on the evaluation result.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Samantha Rao, Zhongsheng Wang, Somvir Singh Dahiya, Chee Lim Nge, Siang Yeong Tan, Chia-Hung S. Kuo
  • Publication number: 20210385942
    Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.
    Type: Application
    Filed: August 10, 2020
    Publication date: December 9, 2021
    Inventors: Tai Loong Wong, Fern Nee Tan, Tin Poay Chuah, Min Suet Lim, Siang Yeong Tan
  • Patent number: 11096284
    Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Wee Hoe, Chan Kim Lee, Chee Chun Yee, Mooi Ling Chang, Siang Yeong Tan, Say Thong Tony Tan
  • Publication number: 20200107444
    Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.
    Type: Application
    Filed: June 25, 2019
    Publication date: April 2, 2020
    Inventors: Wee Hoe, CHAN KIM LEE, CHEE CHUN YEE, Mooi Ling Chang, Siang Yeong Tan, Say Thong Tony Tan
  • Publication number: 20180241232
    Abstract: Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.
    Type: Application
    Filed: November 27, 2017
    Publication date: August 23, 2018
    Applicant: INTEL CORPORATION
    Inventors: Siang Yeong TAN, Wee HOE
  • Patent number: 9831693
    Abstract: Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 28, 2017
    Assignee: INTEL CORPORATION
    Inventors: Siang Yeong Tan, Wee Hoe
  • Publication number: 20140132216
    Abstract: Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 15, 2014
    Inventors: Siang Yeong Tan, Wee Hoe