Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder.

Abstract: A circuit and associated method for providing a true random and unclonable output from the circuit. In the circuit and method, an enable signal is received at a first port of a latch, and a data input signal is received at a second port of the latch. Via an inverter coupled to the latch circuit, an inversion signal of output data from the latch is generated. The inversion of the signal is fed to the second port, and the latch circuit and the inverter are operated to provide the true random and unclonable output.

Abstract: A multi-level memory cell NAND structure of a memory device is utilized to extract uniqueness from the memory device. Certain unreliable characteristics of a NAND-based storage are used to generate a true random number sequence. A method for generating such sequence is based on a physically unclonable function (PUF) which is implemented by extracting unique characteristics of a NAND-based memory device using existing firmware procedures.

Abstract: A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.

Abstract: Compact representation for input workloads is generated in a memory system, A memory controller includes firmware (FW) and an encoder including recurrent encoding blocks. Each recurrent encoding block receives one of input commands in an input workload, and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. The last encoding block generates a final hidden state vector as a compact representation vector corresponding to the input commands. The firmware determines a distance function between the compact representation vector and each of multiple compact workload vectors and tunes at least one of firmware parameters based on the determined distances.

Abstract: A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.

Abstract: Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.

Abstract: Compact representation for input workloads is generated in a memory system, A memory controller includes firmware (FW) and an encoder including recurrent encoding blocks. Each recurrent encoding block receives one of input commands in an input workload, and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. The last encoding block generates a final hidden state vector as a compact representation vector corresponding to the input commands. The firmware determines a distance function between the compact representation vector and each of multiple compact workload vectors and tunes at least one of firmware parameters based on the determined distances.

Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder.

Abstract: Compact representation for input workloads is generated in a memory system. The memory system includes a memory device; and a controller including a recurrent neural network coder. The recurrent neural network coder includes an encoder including recurrent encoding blocks. Each recurrent encoding block: receives one of the input commands in an input workload associated with the memory device; and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. A last encoding block generates a final hidden state vector as the compact representation vector.

Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder. It additionally includes a decoding component and a comparator for checking a validity of first and second input data.

Abstract: Memory systems and components thereof perform clustering on workload items. Such a memory system comprises a memory device from which data is read and to which data is written; and a memory controller that receives from a host workload items in a workload sequence, each workload item being defined by at least a start logical block address (LBA) and a length. The memory controller merges sequential workload items in the workload sequence to constitute a single workload item; identifies a start workload item for a candidate cluster; stores the LBA and a hit count of the start workload item in a hash table of the memory controller; identifies an end workload item for the candidate cluster; determines whether the candidate cluster is found in the workload sequence more than a threshold number of times; and, if so, accepts the candidate cluster.

Abstract: Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.

Abstract: A data scrambler scrambles data for a memory system. The scrambler performs an exclusive OR (XOR) operation on data with a pseudorandom number to generate first scrambled data; identifies a state corresponding to the first scrambled data, among multiple states in a set threshold voltage distribution; transitions the first scrambled data from the identified state to another state in response to a program and erase (PE) counter value; and generates second scrambled data using a subset of encoding values corresponding to the another state, among set encoding values for the multiple states.

Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder. It additionally includes a decoding component and a comparator for checking a validity of first and second input data.

Abstract: Multi-level memory cell NAND structure of a memory device is utilized to extract uniqueness from the memory device. Certain unreliable characteristics of NAND-based storage is are used to generate a true random number sequence. A method for generating such sequence is based on physically unclonable function (PUF) which is implemented by extracting unique characteristics of a NAND-based memory device using existing firmware procedures.

Abstract: Systems and methods are provided for predicting commands. A controller of a memory system includes a receiver for sequentially receiving a plurality of commands for the memory device in a plurality of windows, and a control component including a finite state machine for training multiple groups of states based on characteristics of the plurality of windows, and predicting a characteristic of next commands, which is to be received in a next window subsequent to a last window among the plurality of windows, based on the multiple groups of states.

Abstract: Memory systems and components thereof perform clustering on workload items. Such a memory system comprises a memory device from which data is read and to which data is written; and a memory controller that receives from a host workload items in a workload sequence, each workload item being defined by at least a start logical block address (LBA) and a length. The memory controller merges sequential workload items in the workload sequence to constitute a single workload item; identifies a start workload item for a candidate cluster; stores the LBA and a hit count of the start workload item in a hash table of the memory controller; identifies an end workload item for the candidate cluster; determines whether the candidate cluster is found in the workload sequence more than a threshold number of times; and, if so, accepts the candidate cluster.

Abstract: Systems and methods are provided for predicting commands. A controller of a memory system includes a receiver for sequentially receiving a plurality of commands for the memory device in a plurality of windows, and a control component including a finite state machine for training multiple groups of states based on characteristics of the plurality of windows, and predicting a characteristic of next commands, which is to be received in a next window subsequent to a last window among the plurality of windows, based on the multiple groups of states.