Patents by Inventor Siaw-Kang Lai

Siaw-Kang Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658159
    Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
  • Publication number: 20220013505
    Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
  • Patent number: 11164847
    Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
  • Publication number: 20200105722
    Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
  • Patent number: 10416910
    Abstract: One embodiment relates to a method of saving power in a memory subsystem. A first procedure is performed to save memory controller power by changing a clock toggle rate, and a second procedure is performed to save memory subsystem power by changing a clock frequency for the memory subsystem. A third procedure is performed to rebound back to full speed. Another embodiment relates to a memory subsystem which includes a memory controller, a memory, and a physical input/output interface. The memory controller performs at least a first procedure to save memory controller power by changing a clock toggle rate. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 17, 2019
    Assignee: Altera Corporation
    Inventor: Siaw Kang Lai
  • Patent number: 9390039
    Abstract: In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventor: Siaw Kang Lai
  • Publication number: 20140149620
    Abstract: In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Inventor: Siaw Kang Lai
  • Patent number: 8667197
    Abstract: In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: March 4, 2014
    Assignee: Intel Corporation
    Inventor: Siaw Kang Lai
  • Patent number: 8526601
    Abstract: In the present method of implementing functioning of an encryption engine, a plurality of logic blocks are provided, each for running a function. Each function is run based on three variables, each of which may have a first or second value. The function is run with the first variable value selected as having its first value, and with the second and third variables having their actual values. The function is again run with the first variable value selected as having its second value, and again with the second and third variables having their actual values. An actual value of the first variable is determined, and the output of the logic block is determined by the actual value of the first variable.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: September 3, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Atul Garg, Siaw-Kang Lai
  • Publication number: 20120059962
    Abstract: In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Inventor: Siaw Kang Lai
  • Patent number: 7395306
    Abstract: A system and associated methodology for performing a fast add rotate add operation is disclosed. Two separate addition functions conventionally separated by a shift operation are performed as a single operation thereby reducing the number of acts and resources required to perform the add rotate add operation.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: July 1, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Siaw-Kang Lai, Atul Garg
  • Publication number: 20050226409
    Abstract: In the present method of implementing functioning of an encryption engine, a plurality of logic blocks are provided, each for running a function. Each function is run based on three variables, each of which may have a first or second value. The function is run with the first variable value selected as having its first value, and with the second and third variables having their actual values. The function is again run with the first variable value selected as having its second value, and again with the second and third variables having their actual values. An actual value of the first variable is determined, and the output of the logic block is determined by the actual value of the first variable.
    Type: Application
    Filed: April 5, 2004
    Publication date: October 13, 2005
    Inventors: Atul Garg, Siaw-Kang Lai