Abstract: A method for providing an identification of individual smart meters among a plurality of smart meters communicably coupled in a networked grid area based on a unique identification number stored in the memory of the smart meter is provided. The method includes calculating a first value corresponding to the unique identification number, receiving a query message including a second value corresponding to the unique identification number of one of the plurality of smart meters and determining if the first value matches the second value. The method further includes sending a response message including the unique identification number if the first value matches the second value. The method may further include assigning logical identification numbers to each of the smart meters.

Abstract: A method for providing an identification of individual smart meters among a plurality of smart meters communicably coupled in a networked grid area based on a unique identification number stored in the memory of the smart meter is provided. The method includes calculating a first value corresponding to the unique identification number, receiving a query message including a second value corresponding to the unique identification number of one of the plurality of smart meters and determining if the first value matches the second value. The method further includes sending a response message including the unique identification number if the first value matches the second value. The method may further include assigning logical identification numbers to each of the smart meters.

Abstract: A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Abstract: A method and apparatus for queue concatenation have been disclosed.

Abstract: A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Abstract: A method and apparatus for packet cut-though have been disclosed. In packet cut-through mode successive packet fragments are associated an identical logical data flow. This allows, for example, a SPI-4 interface to be able to successively transmit a whole packet for a logical port without intervening by traffic of other logical ports.

Abstract: A method and apparatus for overbooking FIFO memory have been disclosed.

Abstract: A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

Abstract: A method and apparatus for logical identification priority have been disclosed.

Abstract: A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.