Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified fixed-number-random-access mode, in which the memory array can be continuously read or written in response to receiving a fixed number of random access addresses; sequentially receiving the preset fixed number of access addresses via the data/address multiplexing line in succession; sequentially outputting data read in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates read operations, or sequentially receiving data to be written in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates write operations; and ending the mode by receiving an invalid chip enable signal.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified fixed-number-random-access mode, in which the memory array can be continuously read or written in response to receiving a fixed number of random access addresses; sequentially receiving the preset fixed number of access addresses via the data/address multiplexing line in succession; sequentially outputting data read in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates read operations, or sequentially receiving data to be written in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates write operations; and ending the mode by receiving an invalid chip enable signal.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.

Abstract: A semiconductor memory device capable of improving a read characteristic of a sense amplifier and a stored data read method are provided. The semiconductor memory device includes a sense amplifier and a controller. The sense amplifier has a first transistor that clamps a voltage of a bit line, a second transistor that is provided between a voltage node clamped by the first transistor and a reference voltage node, and a third transistor that is inserted between a charge/discharge node and the voltage node clamped by the first transistor. In a first operation mode, the controller turns on the first transistor and the second transistor and turns off the third transistor. In the second operation mode, the third transistor is turned on and in the third operation mode, the first transistor is turned on, the second transistor is turned off, the third transistor is turned on, and the fourth transistor is turned on.

Abstract: A semiconductor memory device capable of improving a read characteristic of a sense amplifier and a stored data read method are provided. The semiconductor memory device includes a sense amplifier and a controller. The sense amplifier has a first transistor that clamps a voltage of a bit line, a second transistor that is provided between a voltage node clamped by the first transistor and a reference voltage node, and a third transistor that is inserted between a charge/discharge node and the voltage node clamped by the first transistor. In a first operation mode, the controller turns on the first transistor and the second transistor and turns off the third transistor. In the second operation mode, the third transistor is turned on and in the third operation mode, the first transistor is turned on, the second transistor is turned off, the third transistor is turned on, and the fourth transistor is turned on.

Abstract: According to one embodiment, a control circuit is configured to perform a first read operation and a second read operation. The control circuit is configured to perform the plurality of first sense operations when applying a first reading voltage to the word line in the first read operation. The control circuit is configured to perform a second sense operation when applying a second reading voltage to the word line in the second read operation. The control circuit is configured to select one of informations read out by the plurality of sense operations based on data stored in adjacent memory cells.