Abstract: Disclosed are a rolling bearing with fully-filled plastic oil and a manufacturing method therefor. A clearance between the existing cage and an outer ring raceway or outer ring flange or/and between the cage and an inner ring raceway or/and inner ring flange is so small that a plastic oil fluid cannot be filled into a free space inside the bearing fully, which not only limits the advantages of plastic oil-lubricated bearings, but also has other negative effects. In the invention, without affecting the performance of the bearing, unilateral radial clearances between the cage and an outer ring and between the cage and an inner ring are increased to over 0.

Abstract: A method and arrangement are described for pick-up point retrieval timing in a vehicle having autonomous parking capabilities. The arrangement may include a communication interface arranged to receive data concerning a desired retrieval time. A processor may be arranged to monitor one or more parameters while the vehicle is performing autonomous driving along a route to a final slot until autonomous parking of the vehicle has been completed. The processor may be further arranged to calculate when to start autonomous return travel in order to be at the pick-up point at the desired retrieval time based on at least one monitored parameter. An actuator may be arranged to initiate autonomous travel to the pick-up point at the calculated return travel start time.

Abstract: A method and arrangement are described for handover warning in a vehicle having autonomous driving capabilities and a vehicle controller configured to control unmanned autonomous travel. A processor may be configured to monitor if there is a need to transition from unmanned autonomous travel to manual control of the vehicle. A detecting arrangement may be configured to monitor a vehicle driver and evaluate the vehicle driver's readiness to assume the act of driving the vehicle. A warning arrangement may be configured to provide warning information when driver-handover is requested by the processor, which warning arrangement may be further configured to adapt warning information timing in respect to the evaluated vehicle driver's readiness to assume the act of driving the vehicle. A warning output system may be configured to output the time adapted warning information to a vehicle passenger compartment.

Abstract: A method and arrangement are described for pick-up point retrieval timing in a vehicle having autonomous parking capabilities. The arrangement may include a communication interface arranged to receive data concerning a desired retrieval time. A processor may be arranged to monitor one or more parameters while the vehicle is performing autonomous driving along a route to a final slot until autonomous parking of the vehicle has been completed. The processor may be further arranged to calculate when to start autonomous return travel in order to be at the pick-up point at the desired retrieval time based on at least one monitored parameter. An actuator may be arranged to initiate autonomous travel to the pick-up point at the calculated return travel start time.

Abstract: A method and arrangement are described for handover warning in a vehicle having autonomous driving capabilities and a vehicle controller configured to control unmanned autonomous travel. A processor may be configured to monitor if there is a need to transition from unmanned autonomous travel to manual control of the vehicle. A detecting arrangement may be configured to monitor a vehicle driver and evaluate the vehicle driver's readiness to assume the act of driving the vehicle. A warning arrangement may be configured to provide warning information when driver-handover is requested by the processor, which warning arrangement may be further configured to adapt warning information timing in respect to the evaluated vehicle driver's readiness to assume the act of driving the vehicle. A warning output system may be configured to output the time adapted warning information to a vehicle passenger compartment.

Abstract: A DC-DC voltage converter has a pair of switching transistors to provide an output voltage and are alternately switched in a boost mode of operation responsive to control signals. An inductor is connected to the pair of switching transistor and has an inductor current flowing there through. A current sensor monitors an input current and generates a current sense signal responsive thereto. Control circuitry generates the control signals to the second pair of switching transistors responsive to the current sense signal, the output voltage and a current limit signal, wherein when the current limit signal indicates the inductor current exceeds a current limit the control signals configure the pair of switching transistors to decrease the inductor current.

Abstract: A buck boost converter generates a regulated output voltage responsive to an input voltage and switching control signals. Switching control circuitry generates the switching control signals responsive to the regulated output voltage, a maximum duty cycle signal and a mode signal. Mode control circuitry generates the maximum duty cycle signal and the mode signal responsive to a buck PWM signal and a boost PWM signal, a first clock signal and a second clock signal phase shifted from the first clock signal by a fixed, programmable amount. A phase shifter generates the first clock signal and the second clock signal responsive to a reference voltage and a synchronization signal.

Abstract: A buck voltage converter comprises an upper switching transistor connected between an input voltage node and a phase node. The upper switching transistor turns on and off responsive to a first drive signal. A lower switching transistor is connected between the phase node and ground. The lower switching transistor turns on and off responsive to a second drive signal. An inductor is connected the phase node and an output voltage node. Control circuitry generates the first drive signal and the second drive signal responsive to a feedback voltage monitored at the output voltage node and a phase at the phase node.

Abstract: A DC-DC voltage converter has a pair of switching transistors to provide an output voltage and are alternately switched in a boost mode of operation responsive to control signals. An inductor is connected to the pair of switching transistor and has an inductor current flowing there through. A current sensor monitors an input current and generates a current sense signal responsive thereto. Control circuitry generates the control signals to the second pair of switching transistors responsive to the current sense signal, the output voltage and a current limit signal, wherein when the current limit signal indicates the inductor current exceeds a current limit the control signals configure the pair of switching transistors to decrease the inductor current.

Abstract: A current sense amplifier includes a high-side current sense amplifier and a low-side current sense amplifier. The high-side current sense amplifier provides a current sense voltage signal for use with a voltage regulator and generates the current sense voltage signal responsive to a first current sensed through a high-side switching transistor in a first mode when the high-side switching transistor is turned on and the low-side switching transistor is turned off. The high-side current sense amplifier generates the current sense voltage signal responsive to a second current through the low-side switching transistor in a second mode when the low-side switching transistor is turned on and the high-side switching transistor is turned off. The low-side current sense amplifier senses the second current through the low-side switching transistor and generates a current control signal to the high-side current sense amplifier in the second mode.

Abstract: A buck boost converter generates a regulated output voltage responsive to an input voltage and switching control signals. Switching control circuitry generates the switching control signals responsive to the regulated output voltage, a maximum duty cycle signal and a mode signal. Mode control circuitry generates the maximum duty cycle signal and the mode signal responsive to a buck PWM signal and a boost PWM signal, a first clock signal and a second clock signal phase shifted from the first clock signal by a fixed, programmable amount. A phase shifter generates the first clock signal and the second clock signal responsive to a reference voltage and a synchronization signal.

Abstract: A DC-DC voltage converter has a pair of switching transistors to provide an output voltage and are alternately switched in a boost mode of operation responsive to control signals. An inductor is connected to the pair of switching transistor and has an inductor current flowing there through. A current sensor monitors an input current and generates a current sense signal responsive thereto. Control circuitry generates the control signals to the second pair of switching transistors responsive to the current sense signal, the output voltage and a current limit signal, wherein when the current limit signal indicates the inductor current exceeds a current limit the control signals configure the pair of switching transistors to decrease the inductor current.

Abstract: A buck voltage converter comprises an upper switching transistor connected between an input voltage node and a phase node. The upper switching transistor turns on and off responsive to a first drive signal. A lower switching transistor is connected between the phase node and ground. The lower switching transistor turns on and off responsive to a second drive signal. An inductor is connected the phase node and an output voltage node. Control circuitry generates the first drive signal and the second drive signal responsive to a feedback voltage monitored at the output voltage node and a phase at the phase node.

Abstract: A multi-output DC/DC voltage regulator has a master regulator for providing a first output voltage pulse responsive to an input voltage. The master regulator generates a synchronization signal that ramps from a first level up to a second level and discharges back to the first level responsive to the first output voltage pulse. At least one slave regulator provides a second output voltage pulse responsive the input voltage and a delay signal. The at least one slave regulator includes comparison logic for comparing the synchronization signal with a reference value and generates the delay signal to initiate the second output voltage pulse when the synchronization signal substantially equals the reference value. The first output voltage pulse is delayed from the second output voltage pulse by a selected amount.

Abstract: A composition, its preparation and use for reducing the blood glucose level in a subject, comprising Radix Ginseng, Rhizoma Atractylodis Macrocephalae, Radix Glycyrrhizae, Ginger, and one or more components selected from the group consisting of Tartarian Buckwheat, Rhizoma Phragmitis (Phragmites communis), Radix Trichosanthis, and Folium Mori.

Abstract: An analog OR circuit selects from a plurality of input voltages to supply other circuits within a device, especially battery powered devices, such as portable telecommunications devices. A plurality of input circuits convert the input voltages to current signals which are averaged to generate a reference current signal. A comparison is made between the input current signals and the reference current signal to generate comparison signals which are output to a winner-takes-all circuit or a comparator for selecting the strongest input voltage signal.