Abstract: A High Speed Multiplier/Divider for use with high speed processors that have dedicated adders, registers, controls and logic for performing a multiply operation, a multiply and add operation, and a divide operation. The multiply/divide circuit has capability of multiplying a 16 bit word times a 16 bit word that produces a 32 bit product with divide being the inversed of the multiplication operation and may use signed or unsigned multiply/divide. A Booth algorithm is used to implement the multiply operation and the multiply/divide operations are operating asynchronous, that is, at the completion of one set of operations, the next set is implemented.

Abstract: A high speed data processor obtains its speed through the efficient transfer of information over separate data and instruction busses, prefetching of instructions, dual working memory and architectural arrangements designed for maximum information transfer. The architecture of the data processor is such that data from any of several sources may be, either in combination or separately, channelled directly through an Arithmetic Logic Unit (ALU) so as to provide quick manipulation of the data since no extra iterations are needed in this movement. The processor uses two scratch pad or working memory areas. Both scratch pad memories communicate directly with the ALU so as to provide two operands, one from each memory and for the operation of the ALU. Two independent registers are provided which allow the linkage of computer words to obtain longer words thereby and a resulting higher precision. This linkage is accomplished by mapping and carrying the most significant bit over to the next sequentially mapped word.