Patents by Inventor Siddarth A. Krishnan

Siddarth A. Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395538
    Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 17, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Deepak Kamalanathan, Archana Kumar, Siddarth Krishnan
  • Publication number: 20200357993
    Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.
    Type: Application
    Filed: April 22, 2020
    Publication date: November 12, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
  • Patent number: 10756194
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Publication number: 20200234959
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Publication number: 20200194319
    Abstract: Embodiments described herein relate to semiconductor processing. More specifically, embodiments described herein relate to processing of transparent substrates. A film is deposited on a backside of the transparent substrate. A thickness of the film is determined such that the film reflects particular wavelengths of light and substantially prevents bowing of the substrate. The film provides constructive interference to the particular wavelengths of light.
    Type: Application
    Filed: October 25, 2019
    Publication date: June 18, 2020
    Inventors: Sage Toko Garrett DOSHAY, Rutger MEYER TIMMERMAN THIJSSEN, Ludovic GODET, Mingwei ZHU, Naamah ARGAMAN, Wayne MCMILLAN, Siddarth KRISHNAN
  • Patent number: 10665450
    Abstract: Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 26, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yixiong Yang, Paul F. Ma, Wei V. Tang, Wenyu Zhang, Shih Chung Chen, Chen Han Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Naomi Yoshida, Lin Dong, Siddarth Krishnan
  • Patent number: 10615041
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10553498
    Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 10487398
    Abstract: Methods for depositing a film comprising exposing a substrate surface to a metal precursor and a hydrazine derivative to form a metal containing film are described.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 26, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Seshadri Ganguli, Siddarth Krishnan, Paul F. Ma, Sang Ho Yu
  • Publication number: 20190318966
    Abstract: A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10395993
    Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10361132
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruqiang Bao, Takashi Ando, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan
  • Publication number: 20190181011
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10312157
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10249543
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10243055
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Publication number: 20190057863
    Abstract: Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 21, 2019
    Inventors: YIXIONG YANG, PAUL F. MA, WEI V. TANG, WENYU ZHANG, SHIH CHUNG CHEN, CHEN HAN LIN, CHI-CHOU LIN, YI XU, YU LEI, NAOMI YOSHIDA, LIN DONG, SIDDARTH KRISHNAN
  • Patent number: 10192822
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer, Kriteshwar K. Kohli, Siddarth A. Krishnan, Joseph F. Shepard, Jr., Keith Kwong Hon Wong
  • Publication number: 20190027572
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Application
    Filed: September 24, 2018
    Publication date: January 24, 2019
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Publication number: 20180330996
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan