Patents by Inventor Siddarth A. Krishnan
Siddarth A. Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10756194Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.Type: GrantFiled: September 24, 2018Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10553498Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.Type: GrantFiled: December 1, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Siddarth A. Krishnan
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Patent number: 10361132Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.Type: GrantFiled: March 31, 2017Date of Patent: July 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruqiang Bao, Takashi Ando, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan
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Patent number: 10312157Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.Type: GrantFiled: October 27, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10249543Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.Type: GrantFiled: October 27, 2017Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10243055Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.Type: GrantFiled: February 28, 2018Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10192822Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.Type: GrantFiled: February 16, 2015Date of Patent: January 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Domingo A. Ferrer, Kriteshwar K. Kohli, Siddarth A. Krishnan, Joseph F. Shepard, Jr., Keith Kwong Hon Wong
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Publication number: 20190027572Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Publication number: 20180330996Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10079182Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.Type: GrantFiled: January 15, 2016Date of Patent: September 18, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10074574Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.Type: GrantFiled: December 1, 2017Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Siddarth A. Krishnan
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Publication number: 20180190784Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.Type: ApplicationFiled: February 28, 2018Publication date: July 5, 2018Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 10002937Abstract: Semiconductor devices and methods of forming the same include forming a work function stack over semiconductor fins in a first region and a second region, the work function stack having a bottom layer, a middle layer, and a top layer. The work function stack is etched to remove the top layer and to decrease a thickness of the middle layer in the second region, leaving a portion of the middle layer and the bottom layer intact. A gate is formed over the semiconductor fins in the first and second regions.Type: GrantFiled: June 8, 2016Date of Patent: June 19, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 9960233Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.Type: GrantFiled: May 22, 2017Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
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Publication number: 20180102294Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.Type: ApplicationFiled: December 1, 2017Publication date: April 12, 2018Inventors: Ruqiang Bao, Siddarth A. Krishnan
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Publication number: 20180096900Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.Type: ApplicationFiled: December 1, 2017Publication date: April 5, 2018Inventors: Ruqiang Bao, Siddarth A. Krishnan
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Patent number: 9922884Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.Type: GrantFiled: October 14, 2015Date of Patent: March 20, 2018Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Siddarth A. Krishnan
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Patent number: 9905476Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.Type: GrantFiled: January 23, 2017Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
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Publication number: 20180047640Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Publication number: 20180047639Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan