Patents by Inventor Siddarth Krishnan

Siddarth Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230015781
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
  • Publication number: 20220310531
    Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
  • Publication number: 20220254886
    Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 ?m. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 11, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Ashish Pal, El Mehdi Bazizi, Siddarth Krishnan, Xing Chen, Lan Yu, Tyler Sherwood
  • Patent number: 11410873
    Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: August 9, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
  • Patent number: 11362275
    Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
  • Publication number: 20220165610
    Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 26, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
  • Publication number: 20220165574
    Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 26, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Joshua S. Holt, Lan Yu, Tyler Sherwood, Archana Kumar, Nicolas Louis Gabriel Breil, Siddarth Krishnan
  • Patent number: 11127458
    Abstract: A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 21, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Deepak Kamalanathan, Siddarth Krishnan, Fuxi Cai, Christophe J Chevallier
  • Publication number: 20210280247
    Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Deepak Kamalanathan, Siddarth Krishnan, Archana Kumar, Fuxi Cai, Federico Nardi
  • Patent number: 11049722
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 11017856
    Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: May 25, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Deepak Kamalanathan, Siddarth Krishnan, Archana Kumar, Fuxi Cai, Federico Nardi
  • Publication number: 20200395538
    Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 17, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Deepak Kamalanathan, Archana Kumar, Siddarth Krishnan
  • Publication number: 20200357993
    Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.
    Type: Application
    Filed: April 22, 2020
    Publication date: November 12, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
  • Patent number: 10756194
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Publication number: 20200234959
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Publication number: 20200194319
    Abstract: Embodiments described herein relate to semiconductor processing. More specifically, embodiments described herein relate to processing of transparent substrates. A film is deposited on a backside of the transparent substrate. A thickness of the film is determined such that the film reflects particular wavelengths of light and substantially prevents bowing of the substrate. The film provides constructive interference to the particular wavelengths of light.
    Type: Application
    Filed: October 25, 2019
    Publication date: June 18, 2020
    Inventors: Sage Toko Garrett DOSHAY, Rutger MEYER TIMMERMAN THIJSSEN, Ludovic GODET, Mingwei ZHU, Naamah ARGAMAN, Wayne MCMILLAN, Siddarth KRISHNAN
  • Patent number: 10665450
    Abstract: Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 26, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yixiong Yang, Paul F. Ma, Wei V. Tang, Wenyu Zhang, Shih Chung Chen, Chen Han Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Naomi Yoshida, Lin Dong, Siddarth Krishnan
  • Patent number: 10615041
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10553498
    Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 10487398
    Abstract: Methods for depositing a film comprising exposing a substrate surface to a metal precursor and a hydrazine derivative to form a metal containing film are described.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 26, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Seshadri Ganguli, Siddarth Krishnan, Paul F. Ma, Sang Ho Yu