Abstract: A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. However, instead of etching a trench in the N-type material to fill with the P-type material, a trench may be etched for both the P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio for the trench. The P-type material may then be formed as a sidewall liner on the trench that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.

Abstract: A method of increasing thermal uniformity of a substrate incorporates high thermal conductivity material in place of shallow trench isolation (STI) dielectric material or interlayer dielectric (ILD) material on a backside of a thinned substrate. The method may comprise removing at least a portion of an STI dielectric material and/or ILD material and depositing a second dielectric material in place of the STI dielectric material that is removed. The second dielectric material has a higher thermal conductivity than the STI dielectric material. The removal may incorporate a wet or dry etch process that is selective to the STI dielectric material and/or the ILD material over other materials used in formation of semiconductor structures on a substrate.

Abstract: Disclosed herein are approaches for forming an air grid of an image sensor. One method may include depositing a first fill material within a first plurality of trenches to form a plurality of grid structures, wherein the first plurality of trenches is formed through an oxide layer formed over a substrate, wherein the fill material is formed along a sidewall and a bottom surface of each trench of the plurality of trenches, and wherein a void is formed within the fill material. The method may further include forming a second plurality of trenches through the oxide layer and the first fill material.

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

Abstract: Methods of processing a substrate are disclosed herein which include treating a surface of a first portion of the substrate to produce a treated substrate having a treated first portion and a second portion, wherein a bonding speed of the treated first portion to another substrate is different than a bonding speed of the second portion to the other substrate. A method of bonding a first substrate to a second substrate is also disclosed.

Abstract: A method of forming a bonded device. The method may include providing a carrier substrate, forming, on a first surface of the carrier substrate, a first bonding layer for bonding to a device substrate, and annealing the first bonding layer at a temperature of greater than 600° C.

Abstract: A method for bonding wafers is provided. More specifically, the method provides for forming a hybrid bond between wafers that compensates for warpage and offset on each of the wafers being bonded.

Abstract: The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.

Abstract: A semiconductor structure including a dielectric film wherein stress has been inducted into one or more stressed portions of the dielectric film to create one or more stress zones. The stress zones correspond to locations of warpage in the semiconductor structure and reduce warpage. In some examples, the stress zones can be created by exposing portions of the dielectric film to different amounts of heat. In some examples, the stress zones can be created by one or more recesses in the dielectric film.

Abstract: A method for forming a structure with a backside power delivery network incorporates a high thermal conductivity material as the bonding layer. In some embodiments, the method may comprise forming a first layer stack that includes a front side metallization (FSM) signal layer formed on a silicon die layer containing nano-through silicon vias (n-TSVs) that is formed on a back side metallization (BSM) power distribution layer where the n-TSVs provide back side power connections to the FSM signal layer, forming a second layer stack that includes a silicon carrier layer, and forming a third layer stack that includes the first layer stack and the second layer stack bonded together with a bonding layer interposed between the first layer stack and the second layer stack where the bonding layer is formed of a cubic-boron nitride-based material.

Abstract: Exemplary semiconductor processing methods may include depositing a first material on a first substrate. The first material may be characterized by a first average surface roughness greater than 5 ?. The methods may include depositing a fill material on the first material. The methods may include planarizing the fill material to form a planarized fill material. The planarized fill material may be characterized by a second average surface roughness less than the first average surface roughness. The methods may include bonding the planarized fill material to a second substrate.

Abstract: Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the silicon-containing precursor. The contacting may deposit a layer of silicon-containing material on the layer of silicon-and-carbon-containing material. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the oxygen-containing precursor.

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Abstract: A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 ?m to about 2 ?m) P-type liner instead of completely filling the trench with P-type material. Inside the P-type liner, the trench may then be filled with a passive fill material. Filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.

Abstract: A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. However, instead of etching a trench in the N-type material to fill with the P-type material, a trench may be etched for both the P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio for the trench. The P-type material may then be formed as a sidewall liner on the trench that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.