Patents by Inventor Siddarth Krishnan
Siddarth Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908914Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.Type: GrantFiled: July 15, 2021Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
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Patent number: 11837285Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.Type: GrantFiled: August 22, 2021Date of Patent: December 5, 2023Assignee: Applied Materials, Inc.Inventors: Christophe J. Chevallier, Siddarth Krishnan
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Patent number: 11830824Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.Type: GrantFiled: March 26, 2021Date of Patent: November 28, 2023Assignee: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
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Patent number: 11790989Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.Type: GrantFiled: May 24, 2021Date of Patent: October 17, 2023Assignee: Applied Materials, Inc.Inventors: Deepak Kamalanathan, Siddarth Krishnan, Archana Kumar, Fuxi Cai, Federico Nardi
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Patent number: 11769665Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.Type: GrantFiled: January 11, 2022Date of Patent: September 26, 2023Assignee: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Raman Gaire, Tyler Sherwood, Lan Yu, Roger Quon, Siddarth Krishnan
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Publication number: 20230232727Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.Type: ApplicationFiled: March 28, 2023Publication date: July 20, 2023Applicant: Applied Materials, Inc.Inventors: Deepak Kamalanathan, Archana Kumar, Siddarth Krishnan
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Patent number: 11705490Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 ?m. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.Type: GrantFiled: February 8, 2021Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Siddarth Krishnan, Xing Chen, Lan Yu, Tyler Sherwood
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Publication number: 20230223256Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.Type: ApplicationFiled: January 11, 2022Publication date: July 13, 2023Applicant: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Raman Gaire, Tyler Sherwood, Lan Yu, Roger Quon, Siddarth Krishnan
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Patent number: 11616195Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.Type: GrantFiled: May 26, 2020Date of Patent: March 28, 2023Assignee: Applied Materials, Inc.Inventors: Deepak Kamalanathan, Archana Kumar, Siddarth Krishnan
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Patent number: 11605741Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.Type: GrantFiled: November 23, 2020Date of Patent: March 14, 2023Assignee: Applied Materials, Inc.Inventors: Joshua S. Holt, Lan Yu, Tyler Sherwood, Archana Kumar, Nicolas Louis Gabriel Breil, Siddarth Krishnan
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Publication number: 20230058423Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.Type: ApplicationFiled: August 22, 2021Publication date: February 23, 2023Applicant: Applied Materials, Inc.Inventors: Christophe J. Chevallier, Siddarth Krishnan
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Publication number: 20230015781Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Applicant: Applied Materials, Inc.Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
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Publication number: 20220310531Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
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Publication number: 20220254886Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 ?m. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.Type: ApplicationFiled: February 8, 2021Publication date: August 11, 2022Applicant: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Siddarth Krishnan, Xing Chen, Lan Yu, Tyler Sherwood
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Patent number: 11410873Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.Type: GrantFiled: November 20, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
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Patent number: 11362275Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.Type: GrantFiled: April 22, 2020Date of Patent: June 14, 2022Assignee: Applied Materials, Inc.Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
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Publication number: 20220165574Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.Type: ApplicationFiled: November 23, 2020Publication date: May 26, 2022Applicant: Applied Materials, Inc.Inventors: Joshua S. Holt, Lan Yu, Tyler Sherwood, Archana Kumar, Nicolas Louis Gabriel Breil, Siddarth Krishnan
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Publication number: 20220165610Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Applicant: Applied Materials, Inc.Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
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Patent number: 11127458Abstract: A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.Type: GrantFiled: April 28, 2020Date of Patent: September 21, 2021Assignee: Applied Materials, Inc.Inventors: Deepak Kamalanathan, Siddarth Krishnan, Fuxi Cai, Christophe J Chevallier
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Publication number: 20210280247Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Applicant: Applied Materials, Inc.Inventors: Deepak Kamalanathan, Siddarth Krishnan, Archana Kumar, Fuxi Cai, Federico Nardi